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![Daniel Lezcano](/assets/img/avatar_default.png)
The CLOCKSOURCE_OF_DECLARE macro is used widely for the timers to declare the clocksource at early stage. However, this macro is also used to initialize the clockevent if any, or the clockevent only. It was originally suggested to declare another macro to initialize a clockevent, so in order to separate the two entities even they belong to the same IP. This was not accepted because of the impact on the DT where splitting a clocksource/clockevent definition does not make sense as it is a Linux concept not a hardware description. On the other side, the clocksource has not interrupt declared while the clockevent has, so it is easy from the driver to know if the description is for a clockevent or a clocksource, IOW it could be implemented at the driver level. So instead of dealing with a named clocksource macro, let's use a more generic one: TIMER_OF_DECLARE. The patch has not functional changes. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
210 lines
4.4 KiB
C
210 lines
4.4 KiB
C
/*
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* linux/arch/h8300/kernel/cpu/timer/timer8.c
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*
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* Yoshinori Sato <ysato@users.sourcefoge.jp>
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*
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* 8bit Timer driver
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*
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*/
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/clockchips.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define _8TCR 0
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#define _8TCSR 2
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#define TCORA 4
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#define TCORB 6
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#define _8TCNT 8
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#define CMIEA 6
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#define CMFA 6
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#define FLAG_STARTED (1 << 3)
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#define SCALE 64
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#define bset(b, a) iowrite8(ioread8(a) | (1 << (b)), (a))
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#define bclr(b, a) iowrite8(ioread8(a) & ~(1 << (b)), (a))
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struct timer8_priv {
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struct clock_event_device ced;
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void __iomem *mapbase;
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unsigned long flags;
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unsigned int rate;
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};
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static irqreturn_t timer8_interrupt(int irq, void *dev_id)
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{
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struct timer8_priv *p = dev_id;
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if (clockevent_state_oneshot(&p->ced))
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iowrite16be(0x0000, p->mapbase + _8TCR);
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p->ced.event_handler(&p->ced);
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bclr(CMFA, p->mapbase + _8TCSR);
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return IRQ_HANDLED;
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}
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static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
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{
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if (delta >= 0x10000)
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pr_warn("delta out of range\n");
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bclr(CMIEA, p->mapbase + _8TCR);
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iowrite16be(delta, p->mapbase + TCORA);
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iowrite16be(0x0000, p->mapbase + _8TCNT);
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bclr(CMFA, p->mapbase + _8TCSR);
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bset(CMIEA, p->mapbase + _8TCR);
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}
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static int timer8_enable(struct timer8_priv *p)
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{
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iowrite16be(0xffff, p->mapbase + TCORA);
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iowrite16be(0x0000, p->mapbase + _8TCNT);
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iowrite16be(0x0c02, p->mapbase + _8TCR);
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return 0;
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}
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static int timer8_start(struct timer8_priv *p)
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{
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int ret;
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if ((p->flags & FLAG_STARTED))
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return 0;
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ret = timer8_enable(p);
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if (!ret)
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p->flags |= FLAG_STARTED;
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return ret;
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}
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static void timer8_stop(struct timer8_priv *p)
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{
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iowrite16be(0x0000, p->mapbase + _8TCR);
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}
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static inline struct timer8_priv *ced_to_priv(struct clock_event_device *ced)
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{
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return container_of(ced, struct timer8_priv, ced);
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}
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static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta)
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{
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timer8_start(p);
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timer8_set_next(p, delta);
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}
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static int timer8_clock_event_shutdown(struct clock_event_device *ced)
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{
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timer8_stop(ced_to_priv(ced));
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return 0;
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}
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static int timer8_clock_event_periodic(struct clock_event_device *ced)
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{
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struct timer8_priv *p = ced_to_priv(ced);
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pr_info("%s: used for periodic clock events\n", ced->name);
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timer8_stop(p);
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timer8_clock_event_start(p, (p->rate + HZ/2) / HZ);
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return 0;
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}
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static int timer8_clock_event_oneshot(struct clock_event_device *ced)
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{
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struct timer8_priv *p = ced_to_priv(ced);
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pr_info("%s: used for oneshot clock events\n", ced->name);
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timer8_stop(p);
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timer8_clock_event_start(p, 0x10000);
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return 0;
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}
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static int timer8_clock_event_next(unsigned long delta,
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struct clock_event_device *ced)
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{
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struct timer8_priv *p = ced_to_priv(ced);
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BUG_ON(!clockevent_state_oneshot(ced));
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timer8_set_next(p, delta - 1);
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return 0;
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}
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static struct timer8_priv timer8_priv = {
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.ced = {
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.name = "h8300_8timer",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.rating = 200,
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.set_next_event = timer8_clock_event_next,
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.set_state_shutdown = timer8_clock_event_shutdown,
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.set_state_periodic = timer8_clock_event_periodic,
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.set_state_oneshot = timer8_clock_event_oneshot,
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},
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};
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static int __init h8300_8timer_init(struct device_node *node)
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{
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void __iomem *base;
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int irq, ret;
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struct clk *clk;
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_err("failed to get clock for clockevent\n");
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return PTR_ERR(clk);
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}
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ret = ENXIO;
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base = of_iomap(node, 0);
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if (!base) {
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pr_err("failed to map registers for clockevent\n");
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goto free_clk;
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}
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ret = -EINVAL;
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irq = irq_of_parse_and_map(node, 0);
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if (!irq) {
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pr_err("failed to get irq for clockevent\n");
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goto unmap_reg;
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}
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timer8_priv.mapbase = base;
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timer8_priv.rate = clk_get_rate(clk) / SCALE;
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if (!timer8_priv.rate) {
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pr_err("Failed to get rate for the clocksource\n");
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goto unmap_reg;
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}
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if (request_irq(irq, timer8_interrupt, IRQF_TIMER,
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timer8_priv.ced.name, &timer8_priv) < 0) {
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pr_err("failed to request irq %d for clockevent\n", irq);
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goto unmap_reg;
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}
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clockevents_config_and_register(&timer8_priv.ced,
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timer8_priv.rate, 1, 0x0000ffff);
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return 0;
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unmap_reg:
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iounmap(base);
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free_clk:
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clk_put(clk);
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return ret;
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}
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TIMER_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);
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