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![Daniel Lezcano](/assets/img/avatar_default.png)
The CLOCKSOURCE_OF_DECLARE macro is used widely for the timers to declare the clocksource at early stage. However, this macro is also used to initialize the clockevent if any, or the clockevent only. It was originally suggested to declare another macro to initialize a clockevent, so in order to separate the two entities even they belong to the same IP. This was not accepted because of the impact on the DT where splitting a clocksource/clockevent definition does not make sense as it is a Linux concept not a hardware description. On the other side, the clocksource has not interrupt declared while the clockevent has, so it is easy from the driver to know if the description is for a clockevent or a clocksource, IOW it could be implemented at the driver level. So instead of dealing with a named clocksource macro, let's use a more generic one: TIMER_OF_DECLARE. The patch has not functional changes. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
268 lines
7.1 KiB
C
268 lines
7.1 KiB
C
/*
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* Mediatek SoCs General-Purpose Timer handling.
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*
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* Copyright (C) 2014 Matthias Brugger
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*
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* Matthias Brugger <matthias.bgg@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include <linux/slab.h>
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#define GPT_IRQ_EN_REG 0x00
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#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
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#define GPT_IRQ_ACK_REG 0x08
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#define GPT_IRQ_ACK(val) BIT((val) - 1)
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#define TIMER_CTRL_REG(val) (0x10 * (val))
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#define TIMER_CTRL_OP(val) (((val) & 0x3) << 4)
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#define TIMER_CTRL_OP_ONESHOT (0)
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#define TIMER_CTRL_OP_REPEAT (1)
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#define TIMER_CTRL_OP_FREERUN (3)
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#define TIMER_CTRL_CLEAR (2)
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#define TIMER_CTRL_ENABLE (1)
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#define TIMER_CTRL_DISABLE (0)
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#define TIMER_CLK_REG(val) (0x04 + (0x10 * (val)))
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#define TIMER_CLK_SRC(val) (((val) & 0x1) << 4)
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#define TIMER_CLK_SRC_SYS13M (0)
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#define TIMER_CLK_SRC_RTC32K (1)
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#define TIMER_CLK_DIV1 (0x0)
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#define TIMER_CLK_DIV2 (0x1)
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#define TIMER_CNT_REG(val) (0x08 + (0x10 * (val)))
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#define TIMER_CMP_REG(val) (0x0C + (0x10 * (val)))
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#define GPT_CLK_EVT 1
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#define GPT_CLK_SRC 2
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struct mtk_clock_event_device {
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void __iomem *gpt_base;
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u32 ticks_per_jiffy;
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struct clock_event_device dev;
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};
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static void __iomem *gpt_sched_reg __read_mostly;
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static u64 notrace mtk_read_sched_clock(void)
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{
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return readl_relaxed(gpt_sched_reg);
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}
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static inline struct mtk_clock_event_device *to_mtk_clk(
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struct clock_event_device *c)
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{
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return container_of(c, struct mtk_clock_event_device, dev);
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}
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static void mtk_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer)
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{
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u32 val;
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val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
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writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base +
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TIMER_CTRL_REG(timer));
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}
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static void mtk_clkevt_time_setup(struct mtk_clock_event_device *evt,
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unsigned long delay, u8 timer)
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{
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writel(delay, evt->gpt_base + TIMER_CMP_REG(timer));
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}
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static void mtk_clkevt_time_start(struct mtk_clock_event_device *evt,
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bool periodic, u8 timer)
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{
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u32 val;
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/* Acknowledge interrupt */
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writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG);
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val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
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/* Clear 2 bit timer operation mode field */
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val &= ~TIMER_CTRL_OP(0x3);
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if (periodic)
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val |= TIMER_CTRL_OP(TIMER_CTRL_OP_REPEAT);
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else
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val |= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT);
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writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR,
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evt->gpt_base + TIMER_CTRL_REG(timer));
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}
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static int mtk_clkevt_shutdown(struct clock_event_device *clk)
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{
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mtk_clkevt_time_stop(to_mtk_clk(clk), GPT_CLK_EVT);
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return 0;
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}
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static int mtk_clkevt_set_periodic(struct clock_event_device *clk)
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{
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struct mtk_clock_event_device *evt = to_mtk_clk(clk);
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mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
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mtk_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT);
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mtk_clkevt_time_start(evt, true, GPT_CLK_EVT);
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return 0;
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}
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static int mtk_clkevt_next_event(unsigned long event,
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struct clock_event_device *clk)
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{
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struct mtk_clock_event_device *evt = to_mtk_clk(clk);
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mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
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mtk_clkevt_time_setup(evt, event, GPT_CLK_EVT);
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mtk_clkevt_time_start(evt, false, GPT_CLK_EVT);
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return 0;
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}
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static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id)
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{
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struct mtk_clock_event_device *evt = dev_id;
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/* Acknowledge timer0 irq */
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writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG);
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evt->dev.event_handler(&evt->dev);
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return IRQ_HANDLED;
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}
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static void
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__init mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option)
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{
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writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
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evt->gpt_base + TIMER_CTRL_REG(timer));
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writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1,
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evt->gpt_base + TIMER_CLK_REG(timer));
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writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer));
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writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE,
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evt->gpt_base + TIMER_CTRL_REG(timer));
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}
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static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer)
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{
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u32 val;
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/* Disable all interrupts */
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writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG);
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/* Acknowledge all spurious pending interrupts */
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writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
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val = readl(evt->gpt_base + GPT_IRQ_EN_REG);
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writel(val | GPT_IRQ_ENABLE(timer),
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evt->gpt_base + GPT_IRQ_EN_REG);
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}
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static int __init mtk_timer_init(struct device_node *node)
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{
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struct mtk_clock_event_device *evt;
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struct resource res;
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unsigned long rate = 0;
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struct clk *clk;
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evt = kzalloc(sizeof(*evt), GFP_KERNEL);
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if (!evt)
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return -ENOMEM;
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evt->dev.name = "mtk_tick";
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evt->dev.rating = 300;
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evt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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evt->dev.set_state_shutdown = mtk_clkevt_shutdown;
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evt->dev.set_state_periodic = mtk_clkevt_set_periodic;
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evt->dev.set_state_oneshot = mtk_clkevt_shutdown;
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evt->dev.tick_resume = mtk_clkevt_shutdown;
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evt->dev.set_next_event = mtk_clkevt_next_event;
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evt->dev.cpumask = cpu_possible_mask;
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evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer");
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if (IS_ERR(evt->gpt_base)) {
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pr_err("Can't get resource\n");
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goto err_kzalloc;
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}
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evt->dev.irq = irq_of_parse_and_map(node, 0);
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if (evt->dev.irq <= 0) {
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pr_err("Can't parse IRQ\n");
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goto err_mem;
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}
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_err("Can't get timer clock\n");
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goto err_irq;
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}
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if (clk_prepare_enable(clk)) {
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pr_err("Can't prepare clock\n");
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goto err_clk_put;
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}
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rate = clk_get_rate(clk);
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if (request_irq(evt->dev.irq, mtk_timer_interrupt,
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IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) {
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pr_err("failed to setup irq %d\n", evt->dev.irq);
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goto err_clk_disable;
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}
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evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
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/* Configure clock source */
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mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
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clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC),
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node->name, rate, 300, 32, clocksource_mmio_readl_up);
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gpt_sched_reg = evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC);
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sched_clock_register(mtk_read_sched_clock, 32, rate);
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/* Configure clock event */
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mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
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clockevents_config_and_register(&evt->dev, rate, 0x3,
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0xffffffff);
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mtk_timer_enable_irq(evt, GPT_CLK_EVT);
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return 0;
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err_clk_disable:
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clk_disable_unprepare(clk);
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err_clk_put:
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clk_put(clk);
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err_irq:
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irq_dispose_mapping(evt->dev.irq);
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err_mem:
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iounmap(evt->gpt_base);
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of_address_to_resource(node, 0, &res);
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release_mem_region(res.start, resource_size(&res));
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err_kzalloc:
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kfree(evt);
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return -EINVAL;
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}
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TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_timer_init);
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