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![Daniel Lezcano](/assets/img/avatar_default.png)
The CLOCKSOURCE_OF_DECLARE macro is used widely for the timers to declare the clocksource at early stage. However, this macro is also used to initialize the clockevent if any, or the clockevent only. It was originally suggested to declare another macro to initialize a clockevent, so in order to separate the two entities even they belong to the same IP. This was not accepted because of the impact on the DT where splitting a clocksource/clockevent definition does not make sense as it is a Linux concept not a hardware description. On the other side, the clocksource has not interrupt declared while the clockevent has, so it is easy from the driver to know if the description is for a clockevent or a clocksource, IOW it could be implemented at the driver level. So instead of dealing with a named clocksource macro, let's use a more generic one: TIMER_OF_DECLARE. The patch has not functional changes. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
218 lines
5.7 KiB
C
218 lines
5.7 KiB
C
/*
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* linux/drivers/clocksource/zevio-timer.c
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*
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* Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2, as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/cpumask.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#define IO_CURRENT_VAL 0x00
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#define IO_DIVIDER 0x04
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#define IO_CONTROL 0x08
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#define IO_TIMER1 0x00
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#define IO_TIMER2 0x0C
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#define IO_MATCH_BEGIN 0x18
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#define IO_MATCH(x) (IO_MATCH_BEGIN + ((x) << 2))
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#define IO_INTR_STS 0x00
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#define IO_INTR_ACK 0x00
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#define IO_INTR_MSK 0x04
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#define CNTL_STOP_TIMER (1 << 4)
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#define CNTL_RUN_TIMER (0 << 4)
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#define CNTL_INC (1 << 3)
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#define CNTL_DEC (0 << 3)
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#define CNTL_TOZERO 0
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#define CNTL_MATCH(x) ((x) + 1)
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#define CNTL_FOREVER 7
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/* There are 6 match registers but we only use one. */
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#define TIMER_MATCH 0
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#define TIMER_INTR_MSK (1 << (TIMER_MATCH))
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#define TIMER_INTR_ALL 0x3F
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struct zevio_timer {
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void __iomem *base;
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void __iomem *timer1, *timer2;
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void __iomem *interrupt_regs;
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struct clk *clk;
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struct clock_event_device clkevt;
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struct irqaction clkevt_irq;
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char clocksource_name[64];
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char clockevent_name[64];
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};
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static int zevio_timer_set_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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struct zevio_timer *timer = container_of(dev, struct zevio_timer,
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clkevt);
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writel(delta, timer->timer1 + IO_CURRENT_VAL);
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writel(CNTL_RUN_TIMER | CNTL_DEC | CNTL_MATCH(TIMER_MATCH),
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timer->timer1 + IO_CONTROL);
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return 0;
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}
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static int zevio_timer_shutdown(struct clock_event_device *dev)
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{
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struct zevio_timer *timer = container_of(dev, struct zevio_timer,
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clkevt);
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/* Disable timer interrupts */
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writel(0, timer->interrupt_regs + IO_INTR_MSK);
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writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
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/* Stop timer */
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writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
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return 0;
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}
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static int zevio_timer_set_oneshot(struct clock_event_device *dev)
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{
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struct zevio_timer *timer = container_of(dev, struct zevio_timer,
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clkevt);
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/* Enable timer interrupts */
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writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_MSK);
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writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
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return 0;
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}
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static irqreturn_t zevio_timer_interrupt(int irq, void *dev_id)
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{
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struct zevio_timer *timer = dev_id;
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u32 intr;
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intr = readl(timer->interrupt_regs + IO_INTR_ACK);
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if (!(intr & TIMER_INTR_MSK))
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return IRQ_NONE;
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writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_ACK);
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writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
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if (timer->clkevt.event_handler)
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timer->clkevt.event_handler(&timer->clkevt);
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return IRQ_HANDLED;
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}
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static int __init zevio_timer_add(struct device_node *node)
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{
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struct zevio_timer *timer;
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struct resource res;
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int irqnr, ret;
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timer = kzalloc(sizeof(*timer), GFP_KERNEL);
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if (!timer)
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return -ENOMEM;
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timer->base = of_iomap(node, 0);
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if (!timer->base) {
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ret = -EINVAL;
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goto error_free;
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}
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timer->timer1 = timer->base + IO_TIMER1;
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timer->timer2 = timer->base + IO_TIMER2;
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timer->clk = of_clk_get(node, 0);
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if (IS_ERR(timer->clk)) {
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ret = PTR_ERR(timer->clk);
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pr_err("Timer clock not found! (error %d)\n", ret);
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goto error_unmap;
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}
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timer->interrupt_regs = of_iomap(node, 1);
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irqnr = irq_of_parse_and_map(node, 0);
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of_address_to_resource(node, 0, &res);
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scnprintf(timer->clocksource_name, sizeof(timer->clocksource_name),
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"%llx.%s_clocksource",
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(unsigned long long)res.start, node->name);
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scnprintf(timer->clockevent_name, sizeof(timer->clockevent_name),
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"%llx.%s_clockevent",
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(unsigned long long)res.start, node->name);
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if (timer->interrupt_regs && irqnr) {
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timer->clkevt.name = timer->clockevent_name;
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timer->clkevt.set_next_event = zevio_timer_set_event;
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timer->clkevt.set_state_shutdown = zevio_timer_shutdown;
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timer->clkevt.set_state_oneshot = zevio_timer_set_oneshot;
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timer->clkevt.tick_resume = zevio_timer_set_oneshot;
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timer->clkevt.rating = 200;
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timer->clkevt.cpumask = cpu_all_mask;
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timer->clkevt.features = CLOCK_EVT_FEAT_ONESHOT;
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timer->clkevt.irq = irqnr;
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writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
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writel(0, timer->timer1 + IO_DIVIDER);
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/* Start with timer interrupts disabled */
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writel(0, timer->interrupt_regs + IO_INTR_MSK);
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writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
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/* Interrupt to occur when timer value matches 0 */
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writel(0, timer->base + IO_MATCH(TIMER_MATCH));
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timer->clkevt_irq.name = timer->clockevent_name;
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timer->clkevt_irq.handler = zevio_timer_interrupt;
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timer->clkevt_irq.dev_id = timer;
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timer->clkevt_irq.flags = IRQF_TIMER | IRQF_IRQPOLL;
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setup_irq(irqnr, &timer->clkevt_irq);
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clockevents_config_and_register(&timer->clkevt,
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clk_get_rate(timer->clk), 0x0001, 0xffff);
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pr_info("Added %s as clockevent\n", timer->clockevent_name);
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}
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writel(CNTL_STOP_TIMER, timer->timer2 + IO_CONTROL);
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writel(0, timer->timer2 + IO_CURRENT_VAL);
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writel(0, timer->timer2 + IO_DIVIDER);
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writel(CNTL_RUN_TIMER | CNTL_FOREVER | CNTL_INC,
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timer->timer2 + IO_CONTROL);
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clocksource_mmio_init(timer->timer2 + IO_CURRENT_VAL,
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timer->clocksource_name,
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clk_get_rate(timer->clk),
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200, 16,
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clocksource_mmio_readw_up);
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pr_info("Added %s as clocksource\n", timer->clocksource_name);
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return 0;
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error_unmap:
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iounmap(timer->base);
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error_free:
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kfree(timer);
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return ret;
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}
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static int __init zevio_timer_init(struct device_node *node)
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{
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return zevio_timer_add(node);
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}
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TIMER_OF_DECLARE(zevio_timer, "lsi,zevio-timer", zevio_timer_init);
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