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Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated. Also address the "Programming Note" for optimal performance. Here is the complete text from Oracle SPARC Architecture Specs. 6.3.4.7 DCTI Couples "A delayed control transfer instruction (DCTI) in the delay slot of another DCTI is referred to as a “DCTI couple”. The use of DCTI couples is deprecated in the Oracle SPARC Architecture; no new software should place a DCTI in the delay slot of another DCTI, because on future Oracle SPARC Architecture implementations DCTI couples may execute either slowly or differently than the programmer assumes it will. SPARC V8 and SPARC V9 Compatibility Note The SPARC V8 architecture left behavior undefined for a DCTI couple. The SPARC V9 architecture defined behavior in that case, but as of UltraSPARC Architecture 2005, use of DCTI couples was deprecated. Software should not expect high performance from DCTI couples, and performance of DCTI couples should be expected to decline further in future processors. Programming Note As noted in TABLE 6-5 on page 115, an annulled branch-always (branch-always with a = 1) instruction is not architecturally a DCTI. However, since not all implementations make that distinction, for optimal performance, a DCTI should not be placed in the instruction word immediately following an annulled branch-always instruction (BA,A or BPA,A)." Signed-off-by: Babu Moger <babu.moger@oracle.com> Reviewed-by: Rob Gardner <rob.gardner@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
339 lines
8.8 KiB
ArmAsm
339 lines
8.8 KiB
ArmAsm
/*
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* rtrap.S: Preparing for return from trap on Sparc V9.
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*
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* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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*/
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#include <asm/asi.h>
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#include <asm/pstate.h>
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#include <asm/ptrace.h>
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#include <asm/spitfire.h>
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#include <asm/head.h>
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#include <asm/visasm.h>
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#include <asm/processor.h>
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#ifdef CONFIG_CONTEXT_TRACKING
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# define SCHEDULE_USER schedule_user
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#else
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# define SCHEDULE_USER schedule
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#endif
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.text
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.align 32
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__handle_preemption:
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call SCHEDULE_USER
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wrpr %g0, RTRAP_PSTATE, %pstate
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ba,pt %xcc, __handle_preemption_continue
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wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
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__handle_user_windows:
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call fault_in_user_windows
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wrpr %g0, RTRAP_PSTATE, %pstate
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ba,pt %xcc, __handle_preemption_continue
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wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
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__handle_userfpu:
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rd %fprs, %l5
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andcc %l5, FPRS_FEF, %g0
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sethi %hi(TSTATE_PEF), %o0
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be,a,pn %icc, __handle_userfpu_continue
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andn %l1, %o0, %l1
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ba,a,pt %xcc, __handle_userfpu_continue
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__handle_signal:
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mov %l5, %o1
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add %sp, PTREGS_OFF, %o0
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mov %l0, %o2
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call do_notify_resume
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wrpr %g0, RTRAP_PSTATE, %pstate
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wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
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/* Signal delivery can modify pt_regs tstate, so we must
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* reload it.
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*/
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ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
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sethi %hi(0xf << 20), %l4
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and %l1, %l4, %l4
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ba,pt %xcc, __handle_preemption_continue
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andn %l1, %l4, %l1
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/* When returning from a NMI (%pil==15) interrupt we want to
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* avoid running softirqs, doing IRQ tracing, preempting, etc.
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*/
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.globl rtrap_nmi
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rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
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sethi %hi(0xf << 20), %l4
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and %l1, %l4, %l4
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andn %l1, %l4, %l1
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srl %l4, 20, %l4
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ba,pt %xcc, rtrap_no_irq_enable
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nop
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/* Do not actually set the %pil here. We will do that
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* below after we clear PSTATE_IE in the %pstate register.
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* If we re-enable interrupts here, we can recurse down
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* the hardirq stack potentially endlessly, causing a
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* stack overflow.
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*/
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.align 64
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.globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
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rtrap_irq:
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rtrap:
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/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
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ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
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rtrap_xcall:
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sethi %hi(0xf << 20), %l4
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and %l1, %l4, %l4
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andn %l1, %l4, %l1
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srl %l4, 20, %l4
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#ifdef CONFIG_TRACE_IRQFLAGS
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brnz,pn %l4, rtrap_no_irq_enable
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nop
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call trace_hardirqs_on
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nop
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/* Do not actually set the %pil here. We will do that
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* below after we clear PSTATE_IE in the %pstate register.
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* If we re-enable interrupts here, we can recurse down
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* the hardirq stack potentially endlessly, causing a
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* stack overflow.
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*
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* It is tempting to put this test and trace_hardirqs_on
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* call at the 'rt_continue' label, but that will not work
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* as that path hits unconditionally and we do not want to
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* execute this in NMI return paths, for example.
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*/
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#endif
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rtrap_no_irq_enable:
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andcc %l1, TSTATE_PRIV, %l3
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bne,pn %icc, to_kernel
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nop
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/* We must hold IRQs off and atomically test schedule+signal
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* state, then hold them off all the way back to userspace.
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* If we are returning to kernel, none of this matters. Note
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* that we are disabling interrupts via PSTATE_IE, not using
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* %pil.
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*
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* If we do not do this, there is a window where we would do
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* the tests, later the signal/resched event arrives but we do
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* not process it since we are still in kernel mode. It would
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* take until the next local IRQ before the signal/resched
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* event would be handled.
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*
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* This also means that if we have to deal with user
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* windows, we have to redo all of these sched+signal checks
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* with IRQs disabled.
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*/
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to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
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wrpr 0, %pil
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__handle_preemption_continue:
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ldx [%g6 + TI_FLAGS], %l0
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sethi %hi(_TIF_USER_WORK_MASK), %o0
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or %o0, %lo(_TIF_USER_WORK_MASK), %o0
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andcc %l0, %o0, %g0
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sethi %hi(TSTATE_PEF), %o0
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be,pt %xcc, user_nowork
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andcc %l1, %o0, %g0
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andcc %l0, _TIF_NEED_RESCHED, %g0
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bne,pn %xcc, __handle_preemption
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andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
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bne,pn %xcc, __handle_signal
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ldub [%g6 + TI_WSAVED], %o2
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brnz,pn %o2, __handle_user_windows
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nop
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sethi %hi(TSTATE_PEF), %o0
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andcc %l1, %o0, %g0
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/* This fpdepth clear is necessary for non-syscall rtraps only */
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user_nowork:
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bne,pn %xcc, __handle_userfpu
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stb %g0, [%g6 + TI_FPDEPTH]
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__handle_userfpu_continue:
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rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
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ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
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ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
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ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
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ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
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brz,pt %l3, 1f
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mov %g6, %l2
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/* Must do this before thread reg is clobbered below. */
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LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
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1:
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ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
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ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
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/* Normal globals are restored, go to trap globals. */
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661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
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nop
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
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SET_GL(1)
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.previous
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mov %l2, %g6
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ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
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ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
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ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
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ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
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ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
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ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
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ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
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ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
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ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
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ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
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ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
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wr %o3, %g0, %y
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wrpr %l4, 0x0, %pil
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wrpr %g0, 0x1, %tl
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andn %l1, TSTATE_SYSCALL, %l1
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wrpr %l1, %g0, %tstate
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wrpr %l2, %g0, %tpc
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wrpr %o2, %g0, %tnpc
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brnz,pn %l3, kern_rtt
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mov PRIMARY_CONTEXT, %l7
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661: ldxa [%l7 + %l7] ASI_DMMU, %l0
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.section .sun4v_1insn_patch, "ax"
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.word 661b
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ldxa [%l7 + %l7] ASI_MMU, %l0
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.previous
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sethi %hi(sparc64_kern_pri_nuc_bits), %l1
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ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
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or %l0, %l1, %l0
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661: stxa %l0, [%l7] ASI_DMMU
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.section .sun4v_1insn_patch, "ax"
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.word 661b
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stxa %l0, [%l7] ASI_MMU
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.previous
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sethi %hi(KERNBASE), %l7
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flush %l7
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rdpr %wstate, %l1
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rdpr %otherwin, %l2
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srl %l1, 3, %l1
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wrpr %l2, %g0, %canrestore
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wrpr %l1, %g0, %wstate
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brnz,pt %l2, user_rtt_restore
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wrpr %g0, %g0, %otherwin
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ldx [%g6 + TI_FLAGS], %g3
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wr %g0, ASI_AIUP, %asi
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rdpr %cwp, %g1
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andcc %g3, _TIF_32BIT, %g0
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sub %g1, 1, %g1
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bne,pt %xcc, user_rtt_fill_32bit
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wrpr %g1, %cwp
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ba,a,pt %xcc, user_rtt_fill_64bit
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nop
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user_rtt_fill_fixup_dax:
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ba,pt %xcc, user_rtt_fill_fixup_common
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mov 1, %g3
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user_rtt_fill_fixup_mna:
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ba,pt %xcc, user_rtt_fill_fixup_common
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mov 2, %g3
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user_rtt_fill_fixup:
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ba,pt %xcc, user_rtt_fill_fixup_common
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clr %g3
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user_rtt_pre_restore:
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add %g1, 1, %g1
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wrpr %g1, 0x0, %cwp
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user_rtt_restore:
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restore
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rdpr %canrestore, %g1
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wrpr %g1, 0x0, %cleanwin
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retry
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nop
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kern_rtt: rdpr %canrestore, %g1
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brz,pn %g1, kern_rtt_fill
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nop
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kern_rtt_restore:
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stw %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
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restore
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retry
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to_kernel:
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#ifdef CONFIG_PREEMPT
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ldsw [%g6 + TI_PRE_COUNT], %l5
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brnz %l5, kern_fpucheck
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ldx [%g6 + TI_FLAGS], %l5
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andcc %l5, _TIF_NEED_RESCHED, %g0
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be,pt %xcc, kern_fpucheck
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nop
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cmp %l4, 0
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bne,pn %xcc, kern_fpucheck
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nop
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call preempt_schedule_irq
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nop
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ba,pt %xcc, rtrap
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#endif
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kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
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brz,pt %l5, rt_continue
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srl %l5, 1, %o0
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add %g6, TI_FPSAVED, %l6
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ldub [%l6 + %o0], %l2
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sub %l5, 2, %l5
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add %g6, TI_GSR, %o1
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andcc %l2, (FPRS_FEF|FPRS_DU), %g0
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be,pt %icc, 2f
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and %l2, FPRS_DL, %l6
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andcc %l2, FPRS_FEF, %g0
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be,pn %icc, 5f
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sll %o0, 3, %o5
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rd %fprs, %g1
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wr %g1, FPRS_FEF, %fprs
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ldx [%o1 + %o5], %g1
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add %g6, TI_XFSR, %o1
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sll %o0, 8, %o2
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add %g6, TI_FPREGS, %o3
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brz,pn %l6, 1f
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add %g6, TI_FPREGS+0x40, %o4
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membar #Sync
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ldda [%o3 + %o2] ASI_BLK_P, %f0
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ldda [%o4 + %o2] ASI_BLK_P, %f16
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membar #Sync
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1: andcc %l2, FPRS_DU, %g0
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be,pn %icc, 1f
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wr %g1, 0, %gsr
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add %o2, 0x80, %o2
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membar #Sync
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ldda [%o3 + %o2] ASI_BLK_P, %f32
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ldda [%o4 + %o2] ASI_BLK_P, %f48
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1: membar #Sync
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ldx [%o1 + %o5], %fsr
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2: stb %l5, [%g6 + TI_FPDEPTH]
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ba,pt %xcc, rt_continue
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nop
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5: wr %g0, FPRS_FEF, %fprs
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sll %o0, 8, %o2
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add %g6, TI_FPREGS+0x80, %o3
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add %g6, TI_FPREGS+0xc0, %o4
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membar #Sync
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ldda [%o3 + %o2] ASI_BLK_P, %f32
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ldda [%o4 + %o2] ASI_BLK_P, %f48
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membar #Sync
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wr %g0, FPRS_DU, %fprs
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ba,pt %xcc, rt_continue
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stb %l5, [%g6 + TI_FPDEPTH]
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