Jeremy Linton 2ff075c7df drivers: base: cacheinfo: setup DT cache properties early ... The original intent in cacheinfo was that an architecture specific populate_cache_leaves() would probe the hardware and then cache_shared_cpu_map_setup() and cache_override_properties() would provide firmware help to extend/expand upon what was probed. Arm64 was really the only architecture that was working this way, and with the removal of most of the hardware probing logic it became clear that it was possible to simplify the logic a bit. This patch combines the walk of the DT nodes with the code updating the cache size/line_size and nr_sets. cache_override_properties() (which was DT specific) is then removed. The result is that cacheinfo.of_node is no longer used as a temporary place to hold DT references for future calls that update cache properties. That change helps to clarify its one remaining use (matching cacheinfo nodes that represent shared caches) which will be used by the ACPI/PPTT code in the following patches. Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Vijaya Kumar K <vkilari@codeaurora.org> Tested-by: Xiongfeng Wang <wangxiongfeng2@huawei.com> Tested-by: Tomasz Nowicki <Tomasz.Nowicki@cavium.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>		2018-05-17 17:27:49 +01:00
..
vdso	RISC-V: build vdso-dummy.o with -no-pie	2018-04-24 10:54:46 -07:00
.gitignore	RISC-V: Build Infrastructure	2017-09-26 15:26:49 -07:00
asm-offsets.c	RISC-V: Task implementation	2017-09-26 15:26:46 -07:00
cacheinfo.c	drivers: base: cacheinfo: setup DT cache properties early	2018-05-17 17:27:49 +01:00
cpu.c
cpufeature.c	RISC-V: User-facing API	2017-09-26 15:26:48 -07:00
entry.S	RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler	2018-03-14 21:46:29 +01:00
ftrace.c	riscv/ftrace: Add HAVE_FUNCTION_GRAPH_RET_ADDR_PTR support	2018-04-02 19:59:13 -07:00
head.S	Rename sbi_save to parse_dtb to improve code readability	2018-02-20 10:56:26 -08:00
irq.c	RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler	2018-03-14 21:46:29 +01:00
Makefile	RISC-V: Fixes to module loading	2018-04-02 20:43:14 -07:00
mcount-dyn.S	riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support	2018-04-02 19:59:13 -07:00
mcount.S	riscv/ftrace: Add dynamic function tracer support	2018-04-02 19:59:12 -07:00
module-sections.c	RISC-V: Add section of GOT.PLT for kernel module	2018-04-02 20:00:54 -07:00
module.c	RISC-V: Support SUB32 relocation type in kernel module	2018-04-02 20:00:55 -07:00
module.lds	RISC-V: Add section of GOT.PLT for kernel module	2018-04-02 20:00:54 -07:00
process.c	Merge branch 'work.whack-a-mole' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs	2018-01-31 19:18:12 -08:00
ptrace.c	RISC-V: User-facing API	2017-09-26 15:26:48 -07:00
reset.c
riscv_ksyms.c	RISC-V: Export some expected symbols for modules	2017-11-30 10:01:10 -08:00
setup.c	Rename sbi_save to parse_dtb to improve code readability	2018-02-20 10:56:26 -08:00
signal.c	RISC-V: User-facing API	2017-09-26 15:26:48 -07:00
smp.c	RISC-V: Fixes for clean allmodconfig build	2017-12-01 13:31:31 -08:00
smpboot.c
stacktrace.c	riscv/ftrace: Add HAVE_FUNCTION_GRAPH_RET_ADDR_PTR support	2018-04-02 19:59:13 -07:00
sys_riscv.c	mm: add ksys_mmap_pgoff() helper; remove in-kernel calls to sys_mmap_pgoff()	2018-04-02 20:16:11 +02:00
syscall_table.c	RISC-V: Make __NR_riscv_flush_icache visible to userspace	2018-01-07 15:14:37 -08:00
time.c
traps.c
vdso.c	riscv: remove redundant unlikely()	2018-01-30 19:12:06 -08:00
vmlinux.lds.S	RISC-V: Build Infrastructure	2017-09-26 15:26:49 -07:00