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4e986d3705
It enables VOU VL (Video Layer) to support overlay plane with scaling function. VL0 has some quirks on scaling support. We choose to skip it and only adds VL1 and VL2 into DRM core for now. Function zx_plane_atomic_disable() gets moved around with no changes to save a forward declaration. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Sean Paul <seanpaul@chromium.org>
142 lines
4.5 KiB
C
142 lines
4.5 KiB
C
/*
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* Copyright 2016 Linaro Ltd.
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* Copyright 2016 ZTE Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __ZX_PLANE_REGS_H__
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#define __ZX_PLANE_REGS_H__
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/* GL registers */
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#define GL_CTRL0 0x00
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#define GL_UPDATE BIT(5)
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#define GL_CTRL1 0x04
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#define GL_DATA_FMT_SHIFT 0
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#define GL_DATA_FMT_MASK (0xf << GL_DATA_FMT_SHIFT)
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#define GL_FMT_ARGB8888 0
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#define GL_FMT_RGB888 1
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#define GL_FMT_RGB565 2
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#define GL_FMT_ARGB1555 3
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#define GL_FMT_ARGB4444 4
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#define GL_CTRL2 0x08
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#define GL_GLOBAL_ALPHA_SHIFT 8
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#define GL_GLOBAL_ALPHA_MASK (0xff << GL_GLOBAL_ALPHA_SHIFT)
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#define GL_CTRL3 0x0c
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#define GL_SCALER_BYPASS_MODE BIT(0)
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#define GL_STRIDE 0x18
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#define GL_ADDR 0x1c
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#define GL_SRC_SIZE 0x38
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#define GL_SRC_W_SHIFT 16
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#define GL_SRC_W_MASK (0x3fff << GL_SRC_W_SHIFT)
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#define GL_SRC_H_SHIFT 0
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#define GL_SRC_H_MASK (0x3fff << GL_SRC_H_SHIFT)
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#define GL_POS_START 0x9c
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#define GL_POS_END 0xa0
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#define GL_POS_X_SHIFT 16
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#define GL_POS_X_MASK (0x1fff << GL_POS_X_SHIFT)
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#define GL_POS_Y_SHIFT 0
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#define GL_POS_Y_MASK (0x1fff << GL_POS_Y_SHIFT)
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#define GL_SRC_W(x) (((x) << GL_SRC_W_SHIFT) & GL_SRC_W_MASK)
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#define GL_SRC_H(x) (((x) << GL_SRC_H_SHIFT) & GL_SRC_H_MASK)
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#define GL_POS_X(x) (((x) << GL_POS_X_SHIFT) & GL_POS_X_MASK)
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#define GL_POS_Y(x) (((x) << GL_POS_Y_SHIFT) & GL_POS_Y_MASK)
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/* VL registers */
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#define VL_CTRL0 0x00
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#define VL_UPDATE BIT(3)
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#define VL_CTRL1 0x04
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#define VL_YUV420_PLANAR BIT(5)
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#define VL_YUV422_SHIFT 3
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#define VL_YUV422_YUYV (0 << VL_YUV422_SHIFT)
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#define VL_YUV422_YVYU (1 << VL_YUV422_SHIFT)
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#define VL_YUV422_UYVY (2 << VL_YUV422_SHIFT)
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#define VL_YUV422_VYUY (3 << VL_YUV422_SHIFT)
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#define VL_FMT_YUV420 0
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#define VL_FMT_YUV422 1
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#define VL_FMT_YUV420_P010 2
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#define VL_FMT_YUV420_HANTRO 3
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#define VL_FMT_YUV444_8BIT 4
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#define VL_FMT_YUV444_10BIT 5
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#define VL_CTRL2 0x08
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#define VL_SCALER_BYPASS_MODE BIT(0)
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#define VL_STRIDE 0x0c
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#define LUMA_STRIDE_SHIFT 16
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#define LUMA_STRIDE_MASK (0xffff << LUMA_STRIDE_SHIFT)
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#define CHROMA_STRIDE_SHIFT 0
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#define CHROMA_STRIDE_MASK (0xffff << CHROMA_STRIDE_SHIFT)
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#define VL_SRC_SIZE 0x10
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#define VL_Y 0x14
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#define VL_POS_START 0x30
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#define VL_POS_END 0x34
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#define LUMA_STRIDE(x) (((x) << LUMA_STRIDE_SHIFT) & LUMA_STRIDE_MASK)
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#define CHROMA_STRIDE(x) (((x) << CHROMA_STRIDE_SHIFT) & CHROMA_STRIDE_MASK)
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/* CSC registers */
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#define CSC_CTRL0 0x30
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#define CSC_COV_MODE_SHIFT 16
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#define CSC_COV_MODE_MASK (0xffff << CSC_COV_MODE_SHIFT)
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#define CSC_BT601_IMAGE_RGB2YCBCR 0
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#define CSC_BT601_IMAGE_YCBCR2RGB 1
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#define CSC_BT601_VIDEO_RGB2YCBCR 2
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#define CSC_BT601_VIDEO_YCBCR2RGB 3
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#define CSC_BT709_IMAGE_RGB2YCBCR 4
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#define CSC_BT709_IMAGE_YCBCR2RGB 5
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#define CSC_BT709_VIDEO_RGB2YCBCR 6
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#define CSC_BT709_VIDEO_YCBCR2RGB 7
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#define CSC_BT2020_IMAGE_RGB2YCBCR 8
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#define CSC_BT2020_IMAGE_YCBCR2RGB 9
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#define CSC_BT2020_VIDEO_RGB2YCBCR 10
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#define CSC_BT2020_VIDEO_YCBCR2RGB 11
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#define CSC_WORK_ENABLE BIT(0)
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/* RSZ registers */
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#define RSZ_SRC_CFG 0x00
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#define RSZ_DEST_CFG 0x04
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#define RSZ_ENABLE_CFG 0x14
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#define RSZ_VL_LUMA_HOR 0x08
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#define RSZ_VL_LUMA_VER 0x0c
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#define RSZ_VL_CHROMA_HOR 0x10
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#define RSZ_VL_CHROMA_VER 0x14
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#define RSZ_VL_CTRL_CFG 0x18
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#define RSZ_VL_FMT_SHIFT 3
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#define RSZ_VL_FMT_MASK (0x3 << RSZ_VL_FMT_SHIFT)
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#define RSZ_VL_FMT_YCBCR420 (0x0 << RSZ_VL_FMT_SHIFT)
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#define RSZ_VL_FMT_YCBCR422 (0x1 << RSZ_VL_FMT_SHIFT)
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#define RSZ_VL_FMT_YCBCR444 (0x2 << RSZ_VL_FMT_SHIFT)
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#define RSZ_VL_ENABLE_CFG 0x1c
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#define RSZ_VER_SHIFT 16
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#define RSZ_VER_MASK (0xffff << RSZ_VER_SHIFT)
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#define RSZ_HOR_SHIFT 0
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#define RSZ_HOR_MASK (0xffff << RSZ_HOR_SHIFT)
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#define RSZ_VER(x) (((x) << RSZ_VER_SHIFT) & RSZ_VER_MASK)
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#define RSZ_HOR(x) (((x) << RSZ_HOR_SHIFT) & RSZ_HOR_MASK)
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#define RSZ_DATA_STEP_SHIFT 16
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#define RSZ_DATA_STEP_MASK (0xffff << RSZ_DATA_STEP_SHIFT)
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#define RSZ_PARA_STEP_SHIFT 0
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#define RSZ_PARA_STEP_MASK (0xffff << RSZ_PARA_STEP_SHIFT)
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#define RSZ_DATA_STEP(x) (((x) << RSZ_DATA_STEP_SHIFT) & RSZ_DATA_STEP_MASK)
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#define RSZ_PARA_STEP(x) (((x) << RSZ_PARA_STEP_SHIFT) & RSZ_PARA_STEP_MASK)
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/* HBSC registers */
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#define HBSC_SATURATION 0x00
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#define HBSC_HUE 0x04
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#define HBSC_BRIGHT 0x08
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#define HBSC_CONTRAST 0x0c
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#define HBSC_THRESHOLD_COL1 0x10
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#define HBSC_THRESHOLD_COL2 0x14
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#define HBSC_THRESHOLD_COL3 0x18
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#define HBSC_CTRL0 0x28
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#define HBSC_CTRL_EN BIT(2)
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#endif /* __ZX_PLANE_REGS_H__ */
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