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![Huacai Chen](/assets/img/avatar_default.png)
IPI registers of Loongson-3 include IPI_SET, IPI_CLEAR, IPI_STATUS, IPI_EN and IPI_MAILBOX_BUF. Each bit of IPI_STATUS indicate a type of IPI and IPI_EN indicate whether the IPI is enabled. The sender write 1 to IPI_SET bits generate IPIs in IPI_STATUS, and receiver write 1 to bits of IPI_CLEAR to clear IPIs. IPI_MAILBOX_BUF are used to deliver more information about IPIs. Why we change code in arch/mips/loongson/common/setup.c? If without this change, when SMP configured, system cannot boot since it hang at printk() in cgroup_init_early(). The root cause is: console_trylock() \-->down_trylock(&console_sem) \-->raw_spin_unlock_irqrestore(&sem->lock, flags) \-->_raw_spin_unlock_irqrestore()(SMP/UP have different versions) \-->__raw_spin_unlock_irqrestore() (following is the SMP case) \-->do_raw_spin_unlock() \-->arch_spin_unlock() \-->nudge_writes() \-->mb() \-->wbflush() \-->__wbflush() In previous code __wbflush() is initialized in plat_mem_setup(), but cgroup_init_early() is called before plat_mem_setup(). Therefore, In this patch we make changes to avoid boot failure. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6638 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
267 lines
9.5 KiB
C
267 lines
9.5 KiB
C
/*
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* Copyright (C) 2010, 2011, 2012, Lemote, Inc.
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* Author: Chen Huacai, chenhc@lemote.com
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/cpu.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/cpufreq.h>
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#include <asm/processor.h>
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#include <asm/time.h>
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#include <asm/clock.h>
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#include <asm/tlbflush.h>
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#include <loongson.h>
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#include "smp.h"
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/* read a 32bit value from ipi register */
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#define loongson3_ipi_read32(addr) readl(addr)
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/* read a 64bit value from ipi register */
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#define loongson3_ipi_read64(addr) readq(addr)
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/* write a 32bit value to ipi register */
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#define loongson3_ipi_write32(action, addr) \
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do { \
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writel(action, addr); \
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__wbflush(); \
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} while (0)
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/* write a 64bit value to ipi register */
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#define loongson3_ipi_write64(action, addr) \
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do { \
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writeq(action, addr); \
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__wbflush(); \
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} while (0)
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static void *ipi_set0_regs[] = {
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0),
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0),
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0),
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0),
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};
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static void *ipi_clear0_regs[] = {
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0),
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0),
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0),
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0),
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};
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static void *ipi_status0_regs[] = {
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0),
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0),
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0),
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0),
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};
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static void *ipi_en0_regs[] = {
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0),
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0),
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0),
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0),
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};
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static void *ipi_mailbox_buf[] = {
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF),
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF),
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF),
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(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF),
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(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF),
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(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF),
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(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF),
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};
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/*
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* Simple enough, just poke the appropriate ipi register
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*/
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static void loongson3_send_ipi_single(int cpu, unsigned int action)
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{
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loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu]);
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}
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static void
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loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
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{
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unsigned int i;
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for_each_cpu(i, mask)
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loongson3_ipi_write32((u32)action, ipi_set0_regs[i]);
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}
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void loongson3_ipi_interrupt(struct pt_regs *regs)
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{
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int cpu = smp_processor_id();
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unsigned int action;
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/* Load the ipi register to figure out what we're supposed to do */
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action = loongson3_ipi_read32(ipi_status0_regs[cpu]);
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/* Clear the ipi register to clear the interrupt */
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loongson3_ipi_write32((u32)action, ipi_clear0_regs[cpu]);
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if (action & SMP_RESCHEDULE_YOURSELF)
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scheduler_ipi();
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if (action & SMP_CALL_FUNCTION)
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smp_call_function_interrupt();
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}
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/*
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* SMP init and finish on secondary CPUs
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*/
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static void loongson3_init_secondary(void)
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{
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int i;
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unsigned int imask = STATUSF_IP7 | STATUSF_IP6 |
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STATUSF_IP3 | STATUSF_IP2;
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/* Set interrupt mask, but don't enable */
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change_c0_status(ST0_IM, imask);
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for (i = 0; i < loongson_sysconf.nr_cpus; i++)
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loongson3_ipi_write32(0xffffffff, ipi_en0_regs[i]);
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}
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static void loongson3_smp_finish(void)
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{
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write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
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local_irq_enable();
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loongson3_ipi_write64(0,
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(void *)(ipi_mailbox_buf[smp_processor_id()]+0x0));
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pr_info("CPU#%d finished, CP0_ST=%x\n",
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smp_processor_id(), read_c0_status());
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}
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static void __init loongson3_smp_setup(void)
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{
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int i, num;
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init_cpu_possible(cpu_none_mask);
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set_cpu_possible(0, true);
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__cpu_number_map[0] = 0;
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__cpu_logical_map[0] = 0;
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/* For unified kernel, NR_CPUS is the maximum possible value,
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* loongson_sysconf.nr_cpus is the really present value */
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for (i = 1, num = 0; i < loongson_sysconf.nr_cpus; i++) {
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set_cpu_possible(i, true);
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__cpu_number_map[i] = ++num;
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__cpu_logical_map[num] = i;
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}
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pr_info("Detected %i available secondary CPU(s)\n", num);
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}
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static void __init loongson3_prepare_cpus(unsigned int max_cpus)
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{
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}
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/*
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* Setup the PC, SP, and GP of a secondary processor and start it runing!
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*/
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static void loongson3_boot_secondary(int cpu, struct task_struct *idle)
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{
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unsigned long startargs[4];
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pr_info("Booting CPU#%d...\n", cpu);
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/* startargs[] are initial PC, SP and GP for secondary CPU */
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startargs[0] = (unsigned long)&smp_bootstrap;
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startargs[1] = (unsigned long)__KSTK_TOS(idle);
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startargs[2] = (unsigned long)task_thread_info(idle);
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startargs[3] = 0;
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pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
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cpu, startargs[0], startargs[1], startargs[2]);
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loongson3_ipi_write64(startargs[3], (void *)(ipi_mailbox_buf[cpu]+0x18));
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loongson3_ipi_write64(startargs[2], (void *)(ipi_mailbox_buf[cpu]+0x10));
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loongson3_ipi_write64(startargs[1], (void *)(ipi_mailbox_buf[cpu]+0x8));
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loongson3_ipi_write64(startargs[0], (void *)(ipi_mailbox_buf[cpu]+0x0));
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}
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/*
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* Final cleanup after all secondaries booted
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*/
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static void __init loongson3_cpus_done(void)
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{
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}
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struct plat_smp_ops loongson3_smp_ops = {
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.send_ipi_single = loongson3_send_ipi_single,
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.send_ipi_mask = loongson3_send_ipi_mask,
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.init_secondary = loongson3_init_secondary,
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.smp_finish = loongson3_smp_finish,
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.cpus_done = loongson3_cpus_done,
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.boot_secondary = loongson3_boot_secondary,
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.smp_setup = loongson3_smp_setup,
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.prepare_cpus = loongson3_prepare_cpus,
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};
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