632 lines
15 KiB
Plaintext
632 lines
15 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2023 DH electronics GmbH
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*/
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#include "imx6ull-dhcor-som.dtsi"
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/ {
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aliases {
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/delete-property/ spi2;
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/delete-property/ spi3;
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i2c0 = &i2c2;
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i2c1 = &i2c1;
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mmc2 = &usdhc2;
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rtc0 = &rtc_i2c;
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rtc1 = &snvs_rtc;
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serial0 = &uart1;
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serial1 = &uart6; /* DHCOM UART2, special hardware required */
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serial2 = &uart3;
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serial3 = &uart2; /* Use BT UART always as ttymxc3 */
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serial4 = &uart4;
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serial5 = &uart5;
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spi0 = &ecspi1;
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spi1 = &ecspi4; /* DHCOM SPI2, special hardware required */
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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reg_ext_3v3_ref: regulator-ext-3v3-ref {
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compatible = "regulator-fixed";
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regulator-always-on;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "VCC_3V3_REF";
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};
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reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
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compatible = "regulator-fixed";
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regulator-max-microvolt = <5000000>;
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regulator-min-microvolt = <5000000>;
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regulator-name = "usb-otg1-vbus";
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};
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reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
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compatible = "regulator-fixed";
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gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
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regulator-max-microvolt = <5000000>;
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regulator-min-microvolt = <5000000>;
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regulator-name = "usb-otg2-vbus";
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};
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/* SoM with WiFi/BT: WiFi pin WL_REG_ON is connected to a DHCOM GPIO */
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usdhc1_pwrseq: usdhc1-pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; /* GPIO H */
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};
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};
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/* SoM with WiFi/BT: BT pin BT_REG_ON is connected to a DHCOM GPIO */
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&bluetooth {
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shutdown-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */
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};
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&can1 {
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pinctrl-0 = <&pinctrl_flexcan1>;
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pinctrl-names = "default";
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status = "okay";
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};
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/*
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* The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins.
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* Only if this pins are used as CAN interface enable it on board layer.
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*/
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&can2 {
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pinctrl-0 = <&pinctrl_flexcan2>;
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pinctrl-names = "default";
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};
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/* DHCOM SPI1 */
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&ecspi1 {
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cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pinctrl_ecspi1>;
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pinctrl-names = "default";
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status = "okay";
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};
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/*
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* DHCOM SPI2
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* Special hardware required that uses the pins of FEC2. Therefore this SPI
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* interface can only be used if FEC2 is disabled.
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*/
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&ecspi4 {
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cs-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pinctrl_ecspi4>;
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pinctrl-names = "default";
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};
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/* DHCOM ETH1 */
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&fec1 {
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phy-handle = <&mdio2_phy0>;
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phy-mode = "rmii";
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pinctrl-0 = <&pinctrl_fec1>;
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pinctrl-names = "default";
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status = "okay";
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};
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/* DHCOM ETH2 */
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&fec2 {
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phy-handle = <&mdio2_phy1>;
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phy-mode = "rmii";
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pinctrl-0 = <&pinctrl_fec2>;
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pinctrl-names = "default";
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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mdio2_phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */
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"ethernet-phy-ieee802.3-c22";
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reg = <0>;
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clock-names = "rmii-ref";
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clocks = <&clks IMX6UL_CLK_ENET_REF>;
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interrupt-parent = <&gpio5>;
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interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-0 = <&pinctrl_fec1_phy &pinctrl_snvs_fec1_phy>;
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pinctrl-names = "default";
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reset-assert-us = <500>;
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reset-deassert-us = <500>;
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reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
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smsc,disable-energy-detect; /* Make plugin detection reliable */
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};
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mdio2_phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */
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"ethernet-phy-ieee802.3-c22";
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reg = <1>;
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clock-names = "rmii-ref";
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clocks = <&clks IMX6UL_CLK_ENET2_REF>;
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interrupt-parent = <&gpio5>;
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interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-0 = <&pinctrl_fec2_phy &pinctrl_snvs_fec2_phy>;
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pinctrl-names = "default";
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reset-assert-us = <500>;
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reset-deassert-us = <500>;
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reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
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smsc,disable-energy-detect; /* Make plugin detection reliable */
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};
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};
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};
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&gpio1 {
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gpio-line-names =
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"", "", "", "",
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"", "", "", "",
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"", "", "", "DHCOM-INT",
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"", "", "", "",
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"", "", "DHCOM-I", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "";
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pinctrl-0 = <&pinctrl_spi1_switch
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&pinctrl_dhcom_i &pinctrl_dhcom_int>;
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pinctrl-names = "default";
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};
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&gpio4 {
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gpio-line-names =
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "DHCOM-L", "DHCOM-K", "DHCOM-M",
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"DHCOM-J", "DHCOM-U", "DHCOM-T", "DHCOM-S",
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"DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O",
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"DHCOM-N", "", "", "";
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pinctrl-0 = <&pinctrl_dhcom_j &pinctrl_dhcom_k
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&pinctrl_dhcom_l &pinctrl_dhcom_m
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&pinctrl_dhcom_n &pinctrl_dhcom_o
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&pinctrl_dhcom_p &pinctrl_dhcom_q
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&pinctrl_dhcom_r &pinctrl_dhcom_s
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&pinctrl_dhcom_t &pinctrl_dhcom_u>;
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pinctrl-names = "default";
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};
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&gpio5 {
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gpio-line-names =
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"DHCOM-A", "DHCOM-B", "DHCOM-C", "DHCOM-D",
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"DHCOM-E", "", "", "DHCOM-F",
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"DHCOM-G", "DHCOM-H", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "";
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pinctrl-0 = <&pinctrl_snvs_dhcom_a &pinctrl_snvs_dhcom_b
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&pinctrl_snvs_dhcom_c &pinctrl_snvs_dhcom_d
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&pinctrl_snvs_dhcom_e &pinctrl_snvs_dhcom_f
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&pinctrl_snvs_dhcom_g &pinctrl_snvs_dhcom_h>;
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pinctrl-names = "default";
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};
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/* DHCOM I2C2 */
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&i2c1 {
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rtc_i2c: rtc@32 {
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compatible = "microcrystal,rv8803";
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reg = <0x32>;
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};
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/* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH1 */
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eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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pagesize = <16>;
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};
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/* TI ADC101C027 */
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adc@51 {
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compatible = "ti,adc101c";
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reg = <0x51>;
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vref-supply = <®_ext_3v3_ref>;
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};
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/* TI ADC101C027 */
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adc@52 {
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compatible = "ti,adc101c";
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reg = <0x52>;
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vref-supply = <®_ext_3v3_ref>;
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};
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/* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH2 */
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eeprom@53 {
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compatible = "atmel,24c02";
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reg = <0x53>;
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pagesize = <16>;
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};
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};
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/* DHCOM I2C1 */
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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pinctrl-names = "default", "gpio";
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scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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};
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&lcdif {
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pinctrl-0 = <&pinctrl_lcdif>;
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pinctrl-names = "default";
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};
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&pwm1 {
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pinctrl-0 = <&pinctrl_pwm1>;
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pinctrl-names = "default";
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};
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&sai2 {
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assigned-clock-rates = <320000000>;
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assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>;
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pinctrl-0 = <&pinctrl_sai2>;
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pinctrl-names = "default";
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};
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&tsc {
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measure-delay-time = <0xffff>;
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pinctrl-0 = <&pinctrl_tsc>;
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pinctrl-names = "default";
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pre-charge-time = <0xfff>;
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touchscreen-average-samples = <32>;
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xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
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};
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/* DHCOM UART1 */
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&uart1 {
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pinctrl-0 = <&pinctrl_uart1>;
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pinctrl-names = "default";
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status = "okay";
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};
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/*
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* DHCOM UART2 (alternative)
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* Special hardware required that uses DHCOM GPIO pins for DHCOM UART2.
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* Therefore this UART interface can only be used if DHCOM GPIOs J/K/L/M are
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* removed from GPIO hog muxing.
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*/
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&uart6 {
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pinctrl-0 = <&pinctrl_uart6>;
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pinctrl-names = "default";
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uart-has-rtscts;
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};
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&usbotg1 {
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adp-disable;
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disable-over-current;
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dr_mode = "otg";
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hnp-disable;
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pinctrl-0 = <&pinctrl_usbotg1>;
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pinctrl-names = "default";
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srp-disable;
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vbus-supply = <®_usb_otg1_vbus>;
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status = "okay";
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};
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&usbotg2 {
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disable-over-current; /* Overcurrent pin is used for TSC */
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dr_mode = "host";
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pinctrl-0 = <&pinctrl_usbotg2>;
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pinctrl-names = "default";
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tpl-support;
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vbus-supply = <®_usb_otg2_vbus>;
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status = "okay";
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};
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&usbphy1 {
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fsl,tx-d-cal = <106>;
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};
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&usbphy2 {
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fsl,tx-d-cal = <106>;
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};
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/* WiFi on LGA */
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&usdhc1 {
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mmc-pwrseq = <&usdhc1_pwrseq>;
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};
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/* eMMC on module */
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&usdhc2 {
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bus-width = <8>;
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no-1-8-v;
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non-removable;
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pinctrl-0 = <&pinctrl_usdhc2>;
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pinctrl-names = "default";
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vmmc-supply = <&vcc_3v3>;
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vqmmc-supply = <&vcc_3v3>;
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status = "okay";
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};
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&iomuxc {
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/* DHCOM GPIOs I..U + INT_HIGHEST_PRIORITY */
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pinctrl_dhcom_i: dhcom-i-grp {
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fsl,pins = <MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x400120b0>;
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};
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pinctrl_dhcom_j: dhcom-j-grp {
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fsl,pins = <MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x400120b0>;
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};
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pinctrl_dhcom_k: dhcom-k-grp {
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fsl,pins = <MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x400120b0>;
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};
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pinctrl_dhcom_l: dhcom-l-grp {
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fsl,pins = <MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x400120b0>;
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};
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pinctrl_dhcom_m: dhcom-m-grp {
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fsl,pins = <MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x400120b0>;
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};
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pinctrl_dhcom_n: dhcom-n-grp {
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fsl,pins = <MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x400120b0>;
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};
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pinctrl_dhcom_o: dhcom-o-grp {
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fsl,pins = <MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x400120b0>;
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};
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pinctrl_dhcom_p: dhcom-p-grp {
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fsl,pins = <MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x400120b0>;
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};
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pinctrl_dhcom_q: dhcom-q-grp {
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fsl,pins = <MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x400120b0>;
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};
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pinctrl_dhcom_r: dhcom-r-grp {
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fsl,pins = <MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x400120b0>;
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};
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pinctrl_dhcom_s: dhcom-s-grp {
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fsl,pins = <MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x400120b0>;
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};
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pinctrl_dhcom_t: dhcom-t-grp {
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fsl,pins = <MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x400120b0>;
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};
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pinctrl_dhcom_u: dhcom-u-grp {
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fsl,pins = <MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x400120b0>;
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};
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pinctrl_dhcom_int: dhcom-int-grp {
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fsl,pins = <MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x400120b0>;
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};
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pinctrl_ecspi1: ecspi1-grp {
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fsl,pins = <
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MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1
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MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1
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MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1
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MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x1b0b0 /* SS0 */
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>;
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};
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pinctrl_ecspi4: ecspi4-grp {
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fsl,pins = <
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MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x100b1
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MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x100b1
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MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x100b1
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MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* SS0 */
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>;
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};
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pinctrl_fec1: fec1-grp {
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fsl,pins = <
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/* FEC1 uses MDIO bus from FEC2 */
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010
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>;
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};
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pinctrl_fec1_phy: fec1-phy-grp {
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fsl,pins = <
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MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0xb0 /* SMSC PHY reset */
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>;
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};
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pinctrl_fec2: fec2-grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
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MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
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MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010
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MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010
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MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010
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MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010
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>;
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};
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pinctrl_fec2_phy: fec2-phy-grp {
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fsl,pins = <
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MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0xb0 /* SMSC PHY reset */
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>;
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};
|
|
|
|
pinctrl_flexcan1: flexcan1-grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
|
|
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexcan2: flexcan2-grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
|
|
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2c2-grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
|
|
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2_gpio: i2c2-gpio-grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
|
|
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_lcdif: lcdif-grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
|
|
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
|
|
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
|
|
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
|
|
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
|
|
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
|
|
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
|
|
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
|
|
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
|
|
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
|
|
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
|
|
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
|
|
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
|
|
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
|
|
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
|
|
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
|
|
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
|
|
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
|
|
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
|
|
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
|
|
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
|
|
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm1: pwm1-grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_sai2: sai2-grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
|
|
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
|
|
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
|
|
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_tsc: tsc-grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
|
|
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
|
|
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
|
|
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1-grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
|
|
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart6: uart6-grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
|
|
MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
|
|
MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1
|
|
MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbotg1: usbotg1-grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbotg2: usbotg2-grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x120b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2-grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
|
|
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
|
|
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
|
|
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
|
|
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
|
|
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
|
|
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
|
|
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
|
|
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
|
|
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
|
|
MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 /* SD2 Reset */
|
|
>;
|
|
};
|
|
};
|
|
|
|
&iomuxc_snvs {
|
|
/* DHCOM GPIOs A..H */
|
|
pinctrl_snvs_dhcom_a: snvs-dhcom-a-grp {
|
|
fsl,pins = <MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x400120b0>;
|
|
};
|
|
|
|
pinctrl_snvs_dhcom_b: snvs-dhcom-b-grp {
|
|
fsl,pins = <MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x400120b0>;
|
|
};
|
|
|
|
pinctrl_snvs_dhcom_c: snvs-dhcom-c-grp {
|
|
fsl,pins = <MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x400120b0>;
|
|
};
|
|
|
|
pinctrl_snvs_dhcom_d: snvs-dhcom-d-grp {
|
|
fsl,pins = <MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x400120b0>;
|
|
};
|
|
|
|
pinctrl_snvs_dhcom_e: snvs-dhcom-e-grp {
|
|
fsl,pins = <MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x400120b0>;
|
|
};
|
|
|
|
pinctrl_snvs_dhcom_f: snvs-dhcom-f-grp {
|
|
fsl,pins = <MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x400120b0>;
|
|
};
|
|
|
|
pinctrl_snvs_dhcom_g: snvs-dhcom-g-grp {
|
|
fsl,pins = <MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x400120b0>;
|
|
};
|
|
|
|
pinctrl_snvs_dhcom_h: snvs-dhcom-h-grp {
|
|
fsl,pins = <MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400120b0>;
|
|
};
|
|
|
|
pinctrl_snvs_fec1_phy: snvs-fec1-phy-grp {
|
|
fsl,pins = <
|
|
MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0xb1 /* SMSC PHY Int */
|
|
>;
|
|
};
|
|
|
|
pinctrl_snvs_fec2_phy: snvs-fec2-phy-grp {
|
|
fsl,pins = <
|
|
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0xb1 /* SMSC PHY Int */
|
|
>;
|
|
};
|
|
};
|