675 lines
21 KiB
C
675 lines
21 KiB
C
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dccg.h"
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#include "clk_mgr_internal.h"
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// For dce12_get_dp_ref_freq_khz
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#include "dce100/dce_clk_mgr.h"
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// For dcn20_update_clocks_update_dpp_dto
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#include "dcn20/dcn20_clk_mgr.h"
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#include "dcn31/dcn31_clk_mgr.h"
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#include "dcn316_clk_mgr.h"
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#include "reg_helper.h"
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#include "core_types.h"
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#include "dcn316_smu.h"
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#include "dm_helpers.h"
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#include "dc_dmub_srv.h"
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#include "link.h"
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// DCN316 this is CLK1 instance
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#define MAX_INSTANCE 7
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#define MAX_SEGMENT 6
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struct IP_BASE_INSTANCE {
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unsigned int segment[MAX_SEGMENT];
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};
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struct IP_BASE {
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struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
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};
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#define regCLK1_CLK_PLL_REQ 0x0237
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#define regCLK1_CLK_PLL_REQ_BASE_IDX 0
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#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
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#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
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#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
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#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
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#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
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#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
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#define TO_CLK_MGR_DCN316(clk_mgr)\
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container_of(clk_mgr, struct clk_mgr_dcn316, base)
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static int dcn316_get_active_display_cnt_wa(
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struct dc *dc,
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struct dc_state *context)
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{
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int i, display_count;
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bool tmds_present = false;
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display_count = 0;
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for (i = 0; i < context->stream_count; i++) {
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const struct dc_stream_state *stream = context->streams[i];
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if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
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stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
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stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
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tmds_present = true;
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}
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for (i = 0; i < dc->link_count; i++) {
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const struct dc_link *link = dc->links[i];
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/* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
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if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
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link->link_enc->funcs->is_dig_enabled(link->link_enc))
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display_count++;
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}
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/* WA for hang on HDMI after display off back back on*/
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if (display_count == 0 && tmds_present)
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display_count = 1;
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return display_count;
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}
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static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,
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bool safe_to_lower, bool disable)
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{
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struct dc *dc = clk_mgr_base->ctx->dc;
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int i;
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for (i = 0; i < dc->res_pool->pipe_count; ++i) {
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struct pipe_ctx *pipe = safe_to_lower
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? &context->res_ctx.pipe_ctx[i]
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: &dc->current_state->res_ctx.pipe_ctx[i];
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if (pipe->top_pipe || pipe->prev_odm_pipe)
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continue;
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if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) ||
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!pipe->stream->link_enc)) {
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if (disable) {
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if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)
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pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
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reset_sync_context_for_pipe(dc, context, i);
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} else
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pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
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}
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}
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}
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static void dcn316_enable_pme_wa(struct clk_mgr *clk_mgr_base)
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{
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struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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dcn316_smu_enable_pme_wa(clk_mgr);
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}
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static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,
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struct dc_state *context,
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bool safe_to_lower)
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{
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union dmub_rb_cmd cmd;
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struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
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struct dc *dc = clk_mgr_base->ctx->dc;
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int display_count;
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bool update_dppclk = false;
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bool update_dispclk = false;
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bool dpp_clock_lowered = false;
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if (dc->work_arounds.skip_clock_update)
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return;
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/*
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* if it is safe to lower, but we are already in the lower state, we don't have to do anything
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* also if safe to lower is false, we just go in the higher state
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*/
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clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
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if (safe_to_lower) {
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if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
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dcn316_smu_set_dtbclk(clk_mgr, false);
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clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
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}
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/* check that we're not already in lower */
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if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
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display_count = dcn316_get_active_display_cnt_wa(dc, context);
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/* if we can go lower, go lower */
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if (display_count == 0) {
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union display_idle_optimization_u idle_info = { 0 };
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idle_info.idle_info.df_request_disabled = 1;
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idle_info.idle_info.phy_ref_clk_off = 1;
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idle_info.idle_info.s0i2_rdy = 1;
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dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
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/* update power state */
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clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
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}
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}
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} else {
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if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
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dcn316_smu_set_dtbclk(clk_mgr, true);
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clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
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}
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/* check that we're not already in D0 */
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if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
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union display_idle_optimization_u idle_info = { 0 };
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dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
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/* update power state */
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clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
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}
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}
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if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
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clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
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dcn316_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
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}
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if (should_set_clock(safe_to_lower,
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new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
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clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
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dcn316_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
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}
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// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
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if (new_clocks->dppclk_khz < 100000)
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new_clocks->dppclk_khz = 100000;
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if (new_clocks->dispclk_khz < 100000)
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new_clocks->dispclk_khz = 100000;
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if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
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if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
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dpp_clock_lowered = true;
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clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
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update_dppclk = true;
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}
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if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
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dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
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clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
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dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
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dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
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update_dispclk = true;
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}
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if (dpp_clock_lowered) {
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// increase per DPP DTO before lowering global dppclk
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dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
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dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
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} else {
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// increase global DPPCLK before lowering per DPP DTO
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if (update_dppclk || update_dispclk)
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dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
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// always update dtos unless clock is lowered and not safe to lower
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if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
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dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
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}
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// notify DMCUB of latest clocks
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memset(&cmd, 0, sizeof(cmd));
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cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
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cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
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cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
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cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
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clk_mgr_base->clks.dcfclk_deep_sleep_khz;
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cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
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cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
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dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
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}
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static void dcn316_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
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struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
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{
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return;
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}
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static struct clk_bw_params dcn316_bw_params = {
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.vram_type = Ddr4MemType,
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.num_channels = 1,
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.clk_table = {
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.num_entries = 5,
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},
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};
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static struct wm_table ddr4_wm_table = {
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.entries = {
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{
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.wm_inst = WM_A,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.72,
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.sr_exit_time_us = 6.09,
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.sr_enter_plus_exit_time_us = 7.14,
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.valid = true,
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},
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{
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.wm_inst = WM_B,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.72,
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.sr_exit_time_us = 10.12,
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.sr_enter_plus_exit_time_us = 11.48,
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.valid = true,
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},
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{
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.wm_inst = WM_C,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.72,
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.sr_exit_time_us = 10.12,
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.sr_enter_plus_exit_time_us = 11.48,
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.valid = true,
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},
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{
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.wm_inst = WM_D,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.72,
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.sr_exit_time_us = 10.12,
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.sr_enter_plus_exit_time_us = 11.48,
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.valid = true,
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},
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}
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};
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static struct wm_table lpddr5_wm_table = {
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.entries = {
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{
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.wm_inst = WM_A,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.65333,
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.sr_exit_time_us = 11.5,
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.sr_enter_plus_exit_time_us = 14.5,
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.valid = true,
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},
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{
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.wm_inst = WM_B,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.65333,
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.sr_exit_time_us = 11.5,
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.sr_enter_plus_exit_time_us = 14.5,
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.valid = true,
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},
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{
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.wm_inst = WM_C,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.65333,
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.sr_exit_time_us = 11.5,
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.sr_enter_plus_exit_time_us = 14.5,
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.valid = true,
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},
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{
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.wm_inst = WM_D,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.65333,
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.sr_exit_time_us = 11.5,
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.sr_enter_plus_exit_time_us = 14.5,
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.valid = true,
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},
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}
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};
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static DpmClocks_316_t dummy_clocks;
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static struct dcn316_watermarks dummy_wms = { 0 };
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static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn316_watermarks *table)
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{
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int i, num_valid_sets;
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num_valid_sets = 0;
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for (i = 0; i < WM_SET_COUNT; i++) {
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/* skip empty entries, the smu array has no holes*/
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if (!bw_params->wm_table.entries[i].valid)
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continue;
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table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
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table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
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/* We will not select WM based on fclk, so leave it as unconstrained */
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table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
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table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
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if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
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if (i == 0)
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table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
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else {
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/* add 1 to make it non-overlapping with next lvl */
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table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
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bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
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}
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table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
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bw_params->clk_table.entries[i].dcfclk_mhz;
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} else {
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/* unconstrained for memory retraining */
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table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
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table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
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/* Modify previous watermark range to cover up to max */
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table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
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}
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num_valid_sets++;
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}
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ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
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/* modify the min and max to make sure we cover the whole range*/
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table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
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table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
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table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
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table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
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/* This is for writeback only, does not matter currently as no writeback support*/
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table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
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table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
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table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
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table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
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table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
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}
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static void dcn316_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
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{
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struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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struct clk_mgr_dcn316 *clk_mgr_dcn316 = TO_CLK_MGR_DCN316(clk_mgr);
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struct dcn316_watermarks *table = clk_mgr_dcn316->smu_wm_set.wm_set;
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if (!clk_mgr->smu_ver)
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return;
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if (!table || clk_mgr_dcn316->smu_wm_set.mc_address.quad_part == 0)
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return;
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memset(table, 0, sizeof(*table));
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dcn316_build_watermark_ranges(clk_mgr_base->bw_params, table);
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|
|
dcn316_smu_set_dram_addr_high(clk_mgr,
|
|
clk_mgr_dcn316->smu_wm_set.mc_address.high_part);
|
|
dcn316_smu_set_dram_addr_low(clk_mgr,
|
|
clk_mgr_dcn316->smu_wm_set.mc_address.low_part);
|
|
dcn316_smu_transfer_wm_table_dram_2_smu(clk_mgr);
|
|
}
|
|
|
|
static void dcn316_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
|
|
struct dcn316_smu_dpm_clks *smu_dpm_clks)
|
|
{
|
|
DpmClocks_316_t *table = smu_dpm_clks->dpm_clks;
|
|
|
|
if (!clk_mgr->smu_ver)
|
|
return;
|
|
|
|
if (!table || smu_dpm_clks->mc_address.quad_part == 0)
|
|
return;
|
|
|
|
memset(table, 0, sizeof(*table));
|
|
|
|
dcn316_smu_set_dram_addr_high(clk_mgr,
|
|
smu_dpm_clks->mc_address.high_part);
|
|
dcn316_smu_set_dram_addr_low(clk_mgr,
|
|
smu_dpm_clks->mc_address.low_part);
|
|
dcn316_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
|
|
}
|
|
|
|
static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
|
|
{
|
|
uint32_t max = 0;
|
|
int i;
|
|
|
|
for (i = 0; i < num_clocks; ++i) {
|
|
if (clocks[i] > max)
|
|
max = clocks[i];
|
|
}
|
|
|
|
return max;
|
|
}
|
|
|
|
static unsigned int find_clk_for_voltage(
|
|
const DpmClocks_316_t *clock_table,
|
|
const uint32_t clocks[],
|
|
unsigned int voltage)
|
|
{
|
|
int i;
|
|
int max_voltage = 0;
|
|
int clock = 0;
|
|
|
|
for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
|
|
if (clock_table->SocVoltage[i] == voltage) {
|
|
return clocks[i];
|
|
} else if (clock_table->SocVoltage[i] >= max_voltage &&
|
|
clock_table->SocVoltage[i] < voltage) {
|
|
max_voltage = clock_table->SocVoltage[i];
|
|
clock = clocks[i];
|
|
}
|
|
}
|
|
|
|
ASSERT(clock);
|
|
return clock;
|
|
}
|
|
|
|
static void dcn316_clk_mgr_helper_populate_bw_params(
|
|
struct clk_mgr_internal *clk_mgr,
|
|
struct integrated_info *bios_info,
|
|
const DpmClocks_316_t *clock_table)
|
|
{
|
|
int i, j;
|
|
struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
|
|
uint32_t max_dispclk = 0, max_dppclk = 0;
|
|
|
|
j = -1;
|
|
|
|
ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL);
|
|
|
|
/* Find lowest DPM, FCLK is filled in reverse order*/
|
|
|
|
for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
|
|
if (clock_table->DfPstateTable[i].FClk != 0) {
|
|
j = i;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (j == -1) {
|
|
/* clock table is all 0s, just use our own hardcode */
|
|
ASSERT(0);
|
|
return;
|
|
}
|
|
|
|
bw_params->clk_table.num_entries = j + 1;
|
|
|
|
/* dispclk and dppclk can be max at any voltage, same number of levels for both */
|
|
if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
|
|
clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
|
|
max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
|
|
max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
|
|
} else {
|
|
ASSERT(0);
|
|
}
|
|
|
|
for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
|
|
int temp;
|
|
|
|
bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
|
|
bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
|
|
bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
|
|
switch (clock_table->DfPstateTable[j].WckRatio) {
|
|
case WCK_RATIO_1_2:
|
|
bw_params->clk_table.entries[i].wck_ratio = 2;
|
|
break;
|
|
case WCK_RATIO_1_4:
|
|
bw_params->clk_table.entries[i].wck_ratio = 4;
|
|
break;
|
|
default:
|
|
bw_params->clk_table.entries[i].wck_ratio = 1;
|
|
}
|
|
temp = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
|
|
if (temp)
|
|
bw_params->clk_table.entries[i].dcfclk_mhz = temp;
|
|
temp = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
|
|
if (temp)
|
|
bw_params->clk_table.entries[i].socclk_mhz = temp;
|
|
bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
|
|
bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
|
|
}
|
|
|
|
bw_params->vram_type = bios_info->memory_type;
|
|
bw_params->num_channels = bios_info->ma_channel_number;
|
|
bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
|
|
|
|
for (i = 0; i < WM_SET_COUNT; i++) {
|
|
bw_params->wm_table.entries[i].wm_inst = i;
|
|
|
|
if (i >= bw_params->clk_table.num_entries) {
|
|
bw_params->wm_table.entries[i].valid = false;
|
|
continue;
|
|
}
|
|
|
|
bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
|
|
bw_params->wm_table.entries[i].valid = true;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
static struct clk_mgr_funcs dcn316_funcs = {
|
|
.enable_pme_wa = dcn316_enable_pme_wa,
|
|
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
|
|
.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
|
|
.update_clocks = dcn316_update_clocks,
|
|
.init_clocks = dcn31_init_clocks,
|
|
.are_clock_states_equal = dcn31_are_clock_states_equal,
|
|
.notify_wm_ranges = dcn316_notify_wm_ranges
|
|
};
|
|
extern struct clk_mgr_funcs dcn3_fpga_funcs;
|
|
|
|
void dcn316_clk_mgr_construct(
|
|
struct dc_context *ctx,
|
|
struct clk_mgr_dcn316 *clk_mgr,
|
|
struct pp_smu_funcs *pp_smu,
|
|
struct dccg *dccg)
|
|
{
|
|
struct dcn316_smu_dpm_clks smu_dpm_clks = { 0 };
|
|
struct clk_log_info log_info = {0};
|
|
|
|
clk_mgr->base.base.ctx = ctx;
|
|
clk_mgr->base.base.funcs = &dcn316_funcs;
|
|
|
|
clk_mgr->base.pp_smu = pp_smu;
|
|
|
|
clk_mgr->base.dccg = dccg;
|
|
clk_mgr->base.dfs_bypass_disp_clk = 0;
|
|
|
|
clk_mgr->base.dprefclk_ss_percentage = 0;
|
|
clk_mgr->base.dprefclk_ss_divider = 1000;
|
|
clk_mgr->base.ss_on_dprefclk = false;
|
|
clk_mgr->base.dfs_ref_freq_khz = 48000;
|
|
|
|
clk_mgr->smu_wm_set.wm_set = (struct dcn316_watermarks *)dm_helpers_allocate_gpu_mem(
|
|
clk_mgr->base.base.ctx,
|
|
DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
|
|
sizeof(struct dcn316_watermarks),
|
|
&clk_mgr->smu_wm_set.mc_address.quad_part);
|
|
|
|
if (!clk_mgr->smu_wm_set.wm_set) {
|
|
clk_mgr->smu_wm_set.wm_set = &dummy_wms;
|
|
clk_mgr->smu_wm_set.mc_address.quad_part = 0;
|
|
}
|
|
ASSERT(clk_mgr->smu_wm_set.wm_set);
|
|
|
|
smu_dpm_clks.dpm_clks = (DpmClocks_316_t *)dm_helpers_allocate_gpu_mem(
|
|
clk_mgr->base.base.ctx,
|
|
DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
|
|
sizeof(DpmClocks_316_t),
|
|
&smu_dpm_clks.mc_address.quad_part);
|
|
|
|
if (smu_dpm_clks.dpm_clks == NULL) {
|
|
smu_dpm_clks.dpm_clks = &dummy_clocks;
|
|
smu_dpm_clks.mc_address.quad_part = 0;
|
|
}
|
|
|
|
ASSERT(smu_dpm_clks.dpm_clks);
|
|
|
|
clk_mgr->base.smu_ver = dcn316_smu_get_smu_version(&clk_mgr->base);
|
|
|
|
if (clk_mgr->base.smu_ver > 0)
|
|
clk_mgr->base.smu_present = true;
|
|
|
|
// Skip this for now as it did not work on DCN315, renable during bring up
|
|
//clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
|
|
clk_mgr->base.base.dentist_vco_freq_khz = 2500000;
|
|
|
|
/* in case we don't get a value from the register, use default */
|
|
if (clk_mgr->base.base.dentist_vco_freq_khz == 0)
|
|
clk_mgr->base.base.dentist_vco_freq_khz = 2500000; /* 2400MHz */
|
|
|
|
|
|
if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
|
|
dcn316_bw_params.wm_table = lpddr5_wm_table;
|
|
} else {
|
|
dcn316_bw_params.wm_table = ddr4_wm_table;
|
|
}
|
|
/* Saved clocks configured at boot for debug purposes */
|
|
dcn316_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
|
|
&clk_mgr->base.base, &log_info);
|
|
|
|
clk_mgr->base.base.dprefclk_khz = 600000;
|
|
clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base);
|
|
clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;
|
|
dce_clock_read_ss_info(&clk_mgr->base);
|
|
/*clk_mgr->base.dccg->ref_dtbclk_khz =
|
|
dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);*/
|
|
|
|
clk_mgr->base.base.bw_params = &dcn316_bw_params;
|
|
|
|
if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
|
|
dcn316_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
|
|
|
|
if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
|
|
dcn316_clk_mgr_helper_populate_bw_params(
|
|
&clk_mgr->base,
|
|
ctx->dc_bios->integrated_info,
|
|
smu_dpm_clks.dpm_clks);
|
|
}
|
|
}
|
|
|
|
if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
|
|
dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
|
|
smu_dpm_clks.dpm_clks);
|
|
}
|
|
|
|
void dcn316_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
|
|
{
|
|
struct clk_mgr_dcn316 *clk_mgr = TO_CLK_MGR_DCN316(clk_mgr_int);
|
|
|
|
if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
|
|
dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
|
|
clk_mgr->smu_wm_set.wm_set);
|
|
}
|