388 lines
11 KiB
C
388 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved
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*/
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#include <drm/display/drm_dsc_helper.h>
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#include "dpu_kms.h"
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#include "dpu_hw_catalog.h"
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#include "dpu_hwio.h"
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#include "dpu_hw_mdss.h"
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#include "dpu_hw_dsc.h"
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#define DSC_CMN_MAIN_CNF 0x00
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/* DPU_DSC_ENC register offsets */
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#define ENC_DF_CTRL 0x00
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#define ENC_GENERAL_STATUS 0x04
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#define ENC_HSLICE_STATUS 0x08
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#define ENC_OUT_STATUS 0x0C
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#define ENC_INT_STAT 0x10
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#define ENC_INT_CLR 0x14
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#define ENC_INT_MASK 0x18
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#define DSC_MAIN_CONF 0x30
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#define DSC_PICTURE_SIZE 0x34
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#define DSC_SLICE_SIZE 0x38
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#define DSC_MISC_SIZE 0x3C
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#define DSC_HRD_DELAYS 0x40
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#define DSC_RC_SCALE 0x44
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#define DSC_RC_SCALE_INC_DEC 0x48
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#define DSC_RC_OFFSETS_1 0x4C
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#define DSC_RC_OFFSETS_2 0x50
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#define DSC_RC_OFFSETS_3 0x54
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#define DSC_RC_OFFSETS_4 0x58
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#define DSC_FLATNESS_QP 0x5C
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#define DSC_RC_MODEL_SIZE 0x60
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#define DSC_RC_CONFIG 0x64
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#define DSC_RC_BUF_THRESH_0 0x68
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#define DSC_RC_BUF_THRESH_1 0x6C
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#define DSC_RC_BUF_THRESH_2 0x70
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#define DSC_RC_BUF_THRESH_3 0x74
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#define DSC_RC_MIN_QP_0 0x78
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#define DSC_RC_MIN_QP_1 0x7C
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#define DSC_RC_MIN_QP_2 0x80
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#define DSC_RC_MAX_QP_0 0x84
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#define DSC_RC_MAX_QP_1 0x88
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#define DSC_RC_MAX_QP_2 0x8C
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#define DSC_RC_RANGE_BPG_OFFSETS_0 0x90
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#define DSC_RC_RANGE_BPG_OFFSETS_1 0x94
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#define DSC_RC_RANGE_BPG_OFFSETS_2 0x98
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/* DPU_DSC_CTL register offsets */
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#define DSC_CTL 0x00
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#define DSC_CFG 0x04
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#define DSC_DATA_IN_SWAP 0x08
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#define DSC_CLK_CTRL 0x0C
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static int _dsc_calc_output_buf_max_addr(struct dpu_hw_dsc *hw_dsc, int num_softslice)
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{
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int max_addr = 2400 / num_softslice;
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if (hw_dsc->caps->features & BIT(DPU_DSC_NATIVE_42x_EN))
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max_addr /= 2;
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return max_addr - 1;
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};
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static void dpu_hw_dsc_disable_1_2(struct dpu_hw_dsc *hw_dsc)
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{
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struct dpu_hw_blk_reg_map *hw;
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const struct dpu_dsc_sub_blks *sblk;
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if (!hw_dsc)
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return;
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hw = &hw_dsc->hw;
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sblk = hw_dsc->caps->sblk;
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DPU_REG_WRITE(hw, sblk->ctl.base + DSC_CFG, 0);
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DPU_REG_WRITE(hw, sblk->enc.base + ENC_DF_CTRL, 0);
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_MAIN_CONF, 0);
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}
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static void dpu_hw_dsc_config_1_2(struct dpu_hw_dsc *hw_dsc,
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struct drm_dsc_config *dsc,
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u32 mode,
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u32 initial_lines)
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{
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struct dpu_hw_blk_reg_map *hw;
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const struct dpu_dsc_sub_blks *sblk;
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u32 data = 0;
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u32 det_thresh_flatness;
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u32 num_active_slice_per_enc;
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u32 bpp;
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if (!hw_dsc || !dsc)
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return;
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hw = &hw_dsc->hw;
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sblk = hw_dsc->caps->sblk;
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if (mode & DSC_MODE_SPLIT_PANEL)
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data |= BIT(0);
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if (mode & DSC_MODE_MULTIPLEX)
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data |= BIT(1);
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num_active_slice_per_enc = dsc->slice_count;
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if (mode & DSC_MODE_MULTIPLEX)
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num_active_slice_per_enc = dsc->slice_count / 2;
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data |= (num_active_slice_per_enc & 0x3) << 7;
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DPU_REG_WRITE(hw, DSC_CMN_MAIN_CNF, data);
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data = (initial_lines & 0xff);
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if (mode & DSC_MODE_VIDEO)
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data |= BIT(9);
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data |= (_dsc_calc_output_buf_max_addr(hw_dsc, num_active_slice_per_enc) << 18);
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DPU_REG_WRITE(hw, sblk->enc.base + ENC_DF_CTRL, data);
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data = (dsc->dsc_version_minor & 0xf) << 28;
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if (dsc->dsc_version_minor == 0x2) {
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if (dsc->native_422)
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data |= BIT(22);
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if (dsc->native_420)
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data |= BIT(21);
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}
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bpp = dsc->bits_per_pixel;
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/* as per hw requirement bpp should be programmed
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* twice the actual value in case of 420 or 422 encoding
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*/
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if (dsc->native_422 || dsc->native_420)
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bpp = 2 * bpp;
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data |= bpp << 10;
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if (dsc->block_pred_enable)
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data |= BIT(20);
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if (dsc->convert_rgb)
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data |= BIT(4);
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data |= (dsc->line_buf_depth & 0xf) << 6;
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data |= dsc->bits_per_component & 0xf;
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_MAIN_CONF, data);
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data = (dsc->pic_width & 0xffff) |
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((dsc->pic_height & 0xffff) << 16);
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_PICTURE_SIZE, data);
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data = (dsc->slice_width & 0xffff) |
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((dsc->slice_height & 0xffff) << 16);
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_SLICE_SIZE, data);
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_MISC_SIZE,
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(dsc->slice_chunk_size) & 0xffff);
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data = (dsc->initial_xmit_delay & 0xffff) |
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((dsc->initial_dec_delay & 0xffff) << 16);
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_HRD_DELAYS, data);
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_SCALE,
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dsc->initial_scale_value & 0x3f);
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data = (dsc->scale_increment_interval & 0xffff) |
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((dsc->scale_decrement_interval & 0x7ff) << 16);
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_SCALE_INC_DEC, data);
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data = (dsc->first_line_bpg_offset & 0x1f) |
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((dsc->second_line_bpg_offset & 0x1f) << 5);
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_OFFSETS_1, data);
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data = (dsc->nfl_bpg_offset & 0xffff) |
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((dsc->slice_bpg_offset & 0xffff) << 16);
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_OFFSETS_2, data);
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data = (dsc->initial_offset & 0xffff) |
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((dsc->final_offset & 0xffff) << 16);
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_OFFSETS_3, data);
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data = (dsc->nsl_bpg_offset & 0xffff) |
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((dsc->second_line_offset_adj & 0xffff) << 16);
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_OFFSETS_4, data);
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det_thresh_flatness = drm_dsc_flatness_det_thresh(dsc);
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data = (dsc->flatness_min_qp & 0x1f) |
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((dsc->flatness_max_qp & 0x1f) << 5) |
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((det_thresh_flatness & 0xff) << 10);
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_FLATNESS_QP, data);
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MODEL_SIZE,
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(dsc->rc_model_size) & 0xffff);
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data = dsc->rc_edge_factor & 0xf;
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data |= (dsc->rc_quant_incr_limit0 & 0x1f) << 8;
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data |= (dsc->rc_quant_incr_limit1 & 0x1f) << 13;
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data |= (dsc->rc_tgt_offset_high & 0xf) << 20;
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data |= (dsc->rc_tgt_offset_low & 0xf) << 24;
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_CONFIG, data);
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/* program the dsc wrapper */
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data = BIT(0); /* encoder enable */
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if (dsc->native_422)
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data |= BIT(8);
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else if (dsc->native_420)
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data |= BIT(9);
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if (!dsc->convert_rgb)
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data |= BIT(10);
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if (dsc->bits_per_component == 8)
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data |= BIT(11);
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if (mode & DSC_MODE_SPLIT_PANEL)
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data |= BIT(12);
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if (mode & DSC_MODE_MULTIPLEX)
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data |= BIT(13);
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if (!(mode & DSC_MODE_VIDEO))
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data |= BIT(17);
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DPU_REG_WRITE(hw, sblk->ctl.base + DSC_CFG, data);
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}
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static void dpu_hw_dsc_config_thresh_1_2(struct dpu_hw_dsc *hw_dsc,
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struct drm_dsc_config *dsc)
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{
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struct dpu_hw_blk_reg_map *hw;
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const struct dpu_dsc_sub_blks *sblk;
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struct drm_dsc_rc_range_parameters *rc;
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if (!hw_dsc || !dsc)
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return;
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hw = &hw_dsc->hw;
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sblk = hw_dsc->caps->sblk;
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rc = dsc->rc_range_params;
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/*
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* With BUF_THRESH -- 14 in total
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* each register contains 4 thresh values with the last register
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* containing only 2 thresh values
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*/
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_BUF_THRESH_0,
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(dsc->rc_buf_thresh[0] << 0) |
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(dsc->rc_buf_thresh[1] << 8) |
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(dsc->rc_buf_thresh[2] << 16) |
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(dsc->rc_buf_thresh[3] << 24));
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_BUF_THRESH_1,
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(dsc->rc_buf_thresh[4] << 0) |
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(dsc->rc_buf_thresh[5] << 8) |
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(dsc->rc_buf_thresh[6] << 16) |
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(dsc->rc_buf_thresh[7] << 24));
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_BUF_THRESH_2,
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(dsc->rc_buf_thresh[8] << 0) |
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(dsc->rc_buf_thresh[9] << 8) |
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(dsc->rc_buf_thresh[10] << 16) |
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(dsc->rc_buf_thresh[11] << 24));
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_BUF_THRESH_3,
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(dsc->rc_buf_thresh[12] << 0) |
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(dsc->rc_buf_thresh[13] << 8));
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/*
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* with min/max_QP -- 5 bits
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* each register contains 5 min_qp or max_qp for total of 15
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*
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* With BPG_OFFSET -- 6 bits
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* each register contains 5 BPG_offset for total of 15
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*/
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MIN_QP_0,
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(rc[0].range_min_qp << 0) |
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(rc[1].range_min_qp << 5) |
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(rc[2].range_min_qp << 10) |
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(rc[3].range_min_qp << 15) |
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(rc[4].range_min_qp << 20));
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MAX_QP_0,
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(rc[0].range_max_qp << 0) |
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(rc[1].range_max_qp << 5) |
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(rc[2].range_max_qp << 10) |
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(rc[3].range_max_qp << 15) |
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(rc[4].range_max_qp << 20));
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_RANGE_BPG_OFFSETS_0,
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(rc[0].range_bpg_offset << 0) |
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(rc[1].range_bpg_offset << 6) |
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(rc[2].range_bpg_offset << 12) |
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(rc[3].range_bpg_offset << 18) |
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(rc[4].range_bpg_offset << 24));
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MIN_QP_1,
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(rc[5].range_min_qp << 0) |
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(rc[6].range_min_qp << 5) |
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(rc[7].range_min_qp << 10) |
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(rc[8].range_min_qp << 15) |
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(rc[9].range_min_qp << 20));
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MAX_QP_1,
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(rc[5].range_max_qp << 0) |
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(rc[6].range_max_qp << 5) |
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(rc[7].range_max_qp << 10) |
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(rc[8].range_max_qp << 15) |
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(rc[9].range_max_qp << 20));
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_RANGE_BPG_OFFSETS_1,
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(rc[5].range_bpg_offset << 0) |
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(rc[6].range_bpg_offset << 6) |
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(rc[7].range_bpg_offset << 12) |
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(rc[8].range_bpg_offset << 18) |
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(rc[9].range_bpg_offset << 24));
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MIN_QP_2,
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(rc[10].range_min_qp << 0) |
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(rc[11].range_min_qp << 5) |
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(rc[12].range_min_qp << 10) |
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(rc[13].range_min_qp << 15) |
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(rc[14].range_min_qp << 20));
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MAX_QP_2,
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(rc[10].range_max_qp << 0) |
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(rc[11].range_max_qp << 5) |
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(rc[12].range_max_qp << 10) |
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(rc[13].range_max_qp << 15) |
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(rc[14].range_max_qp << 20));
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DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_RANGE_BPG_OFFSETS_2,
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(rc[10].range_bpg_offset << 0) |
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(rc[11].range_bpg_offset << 6) |
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(rc[12].range_bpg_offset << 12) |
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(rc[13].range_bpg_offset << 18) |
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(rc[14].range_bpg_offset << 24));
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}
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static void dpu_hw_dsc_bind_pingpong_blk_1_2(struct dpu_hw_dsc *hw_dsc,
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const enum dpu_pingpong pp)
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{
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struct dpu_hw_blk_reg_map *hw;
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const struct dpu_dsc_sub_blks *sblk;
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int mux_cfg = 0xf; /* Disabled */
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hw = &hw_dsc->hw;
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sblk = hw_dsc->caps->sblk;
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if (pp)
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mux_cfg = (pp - PINGPONG_0) & 0x7;
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DPU_REG_WRITE(hw, sblk->ctl.base + DSC_CTL, mux_cfg);
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}
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static void _setup_dcs_ops_1_2(struct dpu_hw_dsc_ops *ops,
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const unsigned long features)
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{
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ops->dsc_disable = dpu_hw_dsc_disable_1_2;
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ops->dsc_config = dpu_hw_dsc_config_1_2;
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ops->dsc_config_thresh = dpu_hw_dsc_config_thresh_1_2;
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ops->dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk_1_2;
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}
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struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(const struct dpu_dsc_cfg *cfg,
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void __iomem *addr)
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{
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struct dpu_hw_dsc *c;
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c = kzalloc(sizeof(*c), GFP_KERNEL);
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if (!c)
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return ERR_PTR(-ENOMEM);
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c->hw.blk_addr = addr + cfg->base;
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c->hw.log_mask = DPU_DBG_MASK_DSC;
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c->idx = cfg->id;
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c->caps = cfg;
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_setup_dcs_ops_1_2(&c->ops, c->caps->features);
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return c;
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}
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