Hansen 3137f792c5 drm/amd/display: Set phy_mux_sel bit in dmub scratch register ... [Why] B0 has pipe mux for DIGC and DIGD which can be connected to PHYF/PHYG or PHYC/PHY D. [How] Based on chip internal hardware revision id determine it is B0 and set DMUB scratch register so DMUBFW can connect the display pipe is connected correctly to the dig. Cc: Wayne Lin <wayne.lin@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Hansen <Hansen.Dsouza@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-10-28 14:26:16 -04:00
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drm	drm/amd/display: Set phy_mux_sel bit in dmub scratch register	2021-10-28 14:26:16 -04:00
host1x	gpu: host1x: Plug potential memory leak	2021-09-16 18:06:52 +02:00
ipu-v3	Updates to the interrupt core and driver subsystems:	2021-08-30 14:38:37 -07:00
trace
vga	vgaarb: don't pass a cookie to vga_client_register	2021-07-21 10:29:10 +02:00
Makefile