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a2faac3986
Similar to commita6c30873ee("ARM: 8989/1: use .fpu assembler directives instead of assembler arguments"). GCC and GNU binutils support setting the "sub arch" via -march=, -Wa,-march, target function attribute, and .arch assembler directive. Clang was missing support for -Wa,-march=, but this was implemented in clang-13. The behavior of both GCC and Clang is to prefer -Wa,-march= over -march= for assembler and assembler-with-cpp sources, but Clang will warn about the -march= being unused. clang: warning: argument unused during compilation: '-march=armv6k' [-Wunused-command-line-argument] Since most assembler is non-conditionally assembled with one sub arch (modulo arch/arm/delay-loop.S which conditionally is assembled as armv4 based on CONFIG_ARCH_RPC, and arch/arm/mach-at91/pm-suspend.S which is conditionally assembled as armv7-a based on CONFIG_CPU_V7), prefer the .arch assembler directive. Add a few more instances found in compile testing as found by Arnd and Nathan. Link:1d51c699b9Link: https://bugs.llvm.org/show_bug.cgi?id=48894 Link: https://github.com/ClangBuiltLinux/linux/issues/1195 Link: https://github.com/ClangBuiltLinux/linux/issues/1315 Suggested-by: Arnd Bergmann <arnd@arndb.de> Suggested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
159 lines
4 KiB
ArmAsm
159 lines
4 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Coherency fabric: low level functions
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*
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* Copyright (C) 2012 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file implements the assembly function to add a CPU to the
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* coherency fabric. This function is called by each of the secondary
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* CPUs during their early boot in an SMP kernel, this why this
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* function have to callable from assembly. It can also be called by a
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* primary CPU from C code during its boot.
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*/
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#include <linux/linkage.h>
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#define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0
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#define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4
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#include <asm/assembler.h>
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#include <asm/cp15.h>
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.arch armv7-a
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.text
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/*
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* Returns the coherency base address in r1 (r0 is untouched), or 0 if
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* the coherency fabric is not enabled.
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*/
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ENTRY(ll_get_coherency_base)
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mrc p15, 0, r1, c1, c0, 0
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tst r1, #CR_M @ Check MMU bit enabled
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bne 1f
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/*
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* MMU is disabled, use the physical address of the coherency
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* base address, (or 0x0 if the coherency fabric is not mapped)
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*/
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adr r1, 3f
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ldr r3, [r1]
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ldr r1, [r1, r3]
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b 2f
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1:
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/*
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* MMU is enabled, use the virtual address of the coherency
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* base address.
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*/
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ldr r1, =coherency_base
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ldr r1, [r1]
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2:
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ret lr
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ENDPROC(ll_get_coherency_base)
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/*
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* Returns the coherency CPU mask in r3 (r0 is untouched). This
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* coherency CPU mask can be used with the coherency fabric
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* configuration and control registers. Note that the mask is already
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* endian-swapped as appropriate so that the calling functions do not
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* have to care about endianness issues while accessing the coherency
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* fabric registers
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*/
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ENTRY(ll_get_coherency_cpumask)
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mrc p15, 0, r3, cr0, cr0, 5
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and r3, r3, #15
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mov r2, #(1 << 24)
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lsl r3, r2, r3
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ARM_BE8(rev r3, r3)
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ret lr
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ENDPROC(ll_get_coherency_cpumask)
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/*
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* ll_add_cpu_to_smp_group(), ll_enable_coherency() and
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* ll_disable_coherency() use the strex/ldrex instructions while the
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* MMU can be disabled. The Armada XP SoC has an exclusive monitor
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* that tracks transactions to Device and/or SO memory and thanks to
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* that, exclusive transactions are functional even when the MMU is
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* disabled.
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*/
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ENTRY(ll_add_cpu_to_smp_group)
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/*
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* As r0 is not modified by ll_get_coherency_base() and
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* ll_get_coherency_cpumask(), we use it to temporarly save lr
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* and avoid it being modified by the branch and link
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* calls. This function is used very early in the secondary
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* CPU boot, and no stack is available at this point.
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*/
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mov r0, lr
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bl ll_get_coherency_base
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/* Bail out if the coherency is not enabled */
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cmp r1, #0
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reteq r0
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bl ll_get_coherency_cpumask
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mov lr, r0
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add r0, r1, #ARMADA_XP_CFB_CFG_REG_OFFSET
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1:
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ldrex r2, [r0]
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orr r2, r2, r3
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strex r1, r2, [r0]
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cmp r1, #0
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bne 1b
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ret lr
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ENDPROC(ll_add_cpu_to_smp_group)
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ENTRY(ll_enable_coherency)
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/*
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* As r0 is not modified by ll_get_coherency_base() and
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* ll_get_coherency_cpumask(), we use it to temporarly save lr
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* and avoid it being modified by the branch and link
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* calls. This function is used very early in the secondary
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* CPU boot, and no stack is available at this point.
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*/
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mov r0, lr
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bl ll_get_coherency_base
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/* Bail out if the coherency is not enabled */
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cmp r1, #0
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reteq r0
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bl ll_get_coherency_cpumask
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mov lr, r0
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add r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET
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1:
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ldrex r2, [r0]
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orr r2, r2, r3
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strex r1, r2, [r0]
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cmp r1, #0
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bne 1b
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dsb
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mov r0, #0
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ret lr
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ENDPROC(ll_enable_coherency)
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ENTRY(ll_disable_coherency)
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/*
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* As r0 is not modified by ll_get_coherency_base() and
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* ll_get_coherency_cpumask(), we use it to temporarly save lr
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* and avoid it being modified by the branch and link
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* calls. This function is used very early in the secondary
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* CPU boot, and no stack is available at this point.
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*/
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mov r0, lr
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bl ll_get_coherency_base
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/* Bail out if the coherency is not enabled */
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cmp r1, #0
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reteq r0
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bl ll_get_coherency_cpumask
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mov lr, r0
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add r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET
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1:
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ldrex r2, [r0]
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bic r2, r2, r3
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strex r1, r2, [r0]
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cmp r1, #0
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bne 1b
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dsb
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ret lr
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ENDPROC(ll_disable_coherency)
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.align 2
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3:
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.long coherency_phys_base - .
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