mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-26 20:38:12 +00:00
c942fddf87
Based on 3 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [graeme] [gregory] [gg]@[slimlogic] [co] [uk] [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] [based] [on] [twl6030]_[usb] [c] [author] [hema] [hk] [hemahk]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1105 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.202006027@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
452 lines
13 KiB
C
452 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
/*
|
|
* Driver for the Conexant CX23885 PCIe bridge
|
|
*
|
|
* Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
|
|
*/
|
|
|
|
#ifndef _CX23885_REG_H_
|
|
#define _CX23885_REG_H_
|
|
|
|
/*
|
|
Address Map
|
|
0x00000000 -> 0x00009000 TX SRAM (Fifos)
|
|
0x00010000 -> 0x00013c00 RX SRAM CMDS + CDT
|
|
|
|
EACH CMDS struct is 0x80 bytes long
|
|
|
|
DMAx_PTR1 = 0x03040 address of first cluster
|
|
DMAx_PTR2 = 0x10600 address of the CDT
|
|
DMAx_CNT1 = cluster size in (bytes >> 4) -1
|
|
DMAx_CNT2 = total cdt size for all entries >> 3
|
|
|
|
Cluster Descriptor entry = 4 DWORDS
|
|
DWORD 0 -> ptr to cluster
|
|
DWORD 1 Reserved
|
|
DWORD 2 Reserved
|
|
DWORD 3 Reserved
|
|
|
|
Channel manager Data Structure entry = 20 DWORD
|
|
0 IntialProgramCounterLow
|
|
1 IntialProgramCounterHigh
|
|
2 ClusterDescriptorTableBase
|
|
3 ClusterDescriptorTableSize
|
|
4 InstructionQueueBase
|
|
5 InstructionQueueSize
|
|
... Reserved
|
|
19 Reserved
|
|
*/
|
|
|
|
/* Risc Instructions */
|
|
#define RISC_CNT_INC 0x00010000
|
|
#define RISC_CNT_RESET 0x00030000
|
|
#define RISC_IRQ1 0x01000000
|
|
#define RISC_IRQ2 0x02000000
|
|
#define RISC_EOL 0x04000000
|
|
#define RISC_SOL 0x08000000
|
|
#define RISC_WRITE 0x10000000
|
|
#define RISC_SKIP 0x20000000
|
|
#define RISC_JUMP 0x70000000
|
|
#define RISC_SYNC 0x80000000
|
|
#define RISC_RESYNC 0x80008000
|
|
#define RISC_READ 0x90000000
|
|
#define RISC_WRITERM 0xB0000000
|
|
#define RISC_WRITECM 0xC0000000
|
|
#define RISC_WRITECR 0xD0000000
|
|
#define RISC_WRITEC 0x50000000
|
|
#define RISC_READC 0xA0000000
|
|
|
|
|
|
/* Audio and Video Core */
|
|
#define HOST_REG1 0x00000000
|
|
#define HOST_REG2 0x00000001
|
|
#define HOST_REG3 0x00000002
|
|
|
|
/* Chip Configuration Registers */
|
|
#define CHIP_CTRL 0x00000100
|
|
#define AFE_CTRL 0x00000104
|
|
#define VID_PLL_INT_POST 0x00000108
|
|
#define VID_PLL_FRAC 0x0000010C
|
|
#define AUX_PLL_INT_POST 0x00000110
|
|
#define AUX_PLL_FRAC 0x00000114
|
|
#define SYS_PLL_INT_POST 0x00000118
|
|
#define SYS_PLL_FRAC 0x0000011C
|
|
#define PIN_CTRL 0x00000120
|
|
#define AUD_IO_CTRL 0x00000124
|
|
#define AUD_LOCK1 0x00000128
|
|
#define AUD_LOCK2 0x0000012C
|
|
#define POWER_CTRL 0x00000130
|
|
#define AFE_DIAG_CTRL1 0x00000134
|
|
#define AFE_DIAG_CTRL3 0x0000013C
|
|
#define PLL_DIAG_CTRL 0x00000140
|
|
#define AFE_CLK_OUT_CTRL 0x00000144
|
|
#define DLL1_DIAG_CTRL 0x0000015C
|
|
|
|
/* GPIO[23:19] Output Enable */
|
|
#define GPIO2_OUT_EN_REG 0x00000160
|
|
/* GPIO[23:19] Data Registers */
|
|
#define GPIO2 0x00000164
|
|
|
|
#define IFADC_CTRL 0x00000180
|
|
|
|
/* Infrared Remote Registers */
|
|
#define IR_CNTRL_REG 0x00000200
|
|
#define IR_TXCLK_REG 0x00000204
|
|
#define IR_RXCLK_REG 0x00000208
|
|
#define IR_CDUTY_REG 0x0000020C
|
|
#define IR_STAT_REG 0x00000210
|
|
#define IR_IRQEN_REG 0x00000214
|
|
#define IR_FILTR_REG 0x00000218
|
|
#define IR_FIFO_REG 0x0000023C
|
|
|
|
/* Video Decoder Registers */
|
|
#define MODE_CTRL 0x00000400
|
|
#define OUT_CTRL1 0x00000404
|
|
#define OUT_CTRL2 0x00000408
|
|
#define GEN_STAT 0x0000040C
|
|
#define INT_STAT_MASK 0x00000410
|
|
#define LUMA_CTRL 0x00000414
|
|
#define HSCALE_CTRL 0x00000418
|
|
#define VSCALE_CTRL 0x0000041C
|
|
#define CHROMA_CTRL 0x00000420
|
|
#define VBI_LINE_CTRL1 0x00000424
|
|
#define VBI_LINE_CTRL2 0x00000428
|
|
#define VBI_LINE_CTRL3 0x0000042C
|
|
#define VBI_LINE_CTRL4 0x00000430
|
|
#define VBI_LINE_CTRL5 0x00000434
|
|
#define VBI_FC_CFG 0x00000438
|
|
#define VBI_MISC_CFG1 0x0000043C
|
|
#define VBI_MISC_CFG2 0x00000440
|
|
#define VBI_PAY1 0x00000444
|
|
#define VBI_PAY2 0x00000448
|
|
#define VBI_CUST1_CFG1 0x0000044C
|
|
#define VBI_CUST1_CFG2 0x00000450
|
|
#define VBI_CUST1_CFG3 0x00000454
|
|
#define VBI_CUST2_CFG1 0x00000458
|
|
#define VBI_CUST2_CFG2 0x0000045C
|
|
#define VBI_CUST2_CFG3 0x00000460
|
|
#define VBI_CUST3_CFG1 0x00000464
|
|
#define VBI_CUST3_CFG2 0x00000468
|
|
#define VBI_CUST3_CFG3 0x0000046C
|
|
#define HORIZ_TIM_CTRL 0x00000470
|
|
#define VERT_TIM_CTRL 0x00000474
|
|
#define SRC_COMB_CFG 0x00000478
|
|
#define CHROMA_VBIOFF_CFG 0x0000047C
|
|
#define FIELD_COUNT 0x00000480
|
|
#define MISC_TIM_CTRL 0x00000484
|
|
#define DFE_CTRL1 0x00000488
|
|
#define DFE_CTRL2 0x0000048C
|
|
#define DFE_CTRL3 0x00000490
|
|
#define PLL_CTRL 0x00000494
|
|
#define HTL_CTRL 0x00000498
|
|
#define COMB_CTRL 0x0000049C
|
|
#define CRUSH_CTRL 0x000004A0
|
|
#define SOFT_RST_CTRL 0x000004A4
|
|
#define CX885_VERSION 0x000004B4
|
|
#define VBI_PASS_CTRL 0x000004BC
|
|
|
|
/* Audio Decoder Registers */
|
|
/* 8051 Configuration */
|
|
#define DL_CTL 0x00000800
|
|
#define STD_DET_STATUS 0x00000804
|
|
#define STD_DET_CTL 0x00000808
|
|
#define DW8051_INT 0x0000080C
|
|
#define GENERAL_CTL 0x00000810
|
|
#define AAGC_CTL 0x00000814
|
|
#define DEMATRIX_CTL 0x000008CC
|
|
#define PATH1_CTL1 0x000008D0
|
|
#define PATH1_VOL_CTL 0x000008D4
|
|
#define PATH1_EQ_CTL 0x000008D8
|
|
#define PATH1_SC_CTL 0x000008DC
|
|
#define PATH2_CTL1 0x000008E0
|
|
#define PATH2_VOL_CTL 0x000008E4
|
|
#define PATH2_EQ_CTL 0x000008E8
|
|
#define PATH2_SC_CTL 0x000008EC
|
|
|
|
/* Sample Rate Converter */
|
|
#define SRC_CTL 0x000008F0
|
|
#define SRC_LF_COEF 0x000008F4
|
|
#define SRC1_CTL 0x000008F8
|
|
#define SRC2_CTL 0x000008FC
|
|
#define SRC3_CTL 0x00000900
|
|
#define SRC4_CTL 0x00000904
|
|
#define SRC5_CTL 0x00000908
|
|
#define SRC6_CTL 0x0000090C
|
|
#define BAND_OUT_SEL 0x00000910
|
|
#define I2S_N_CTL 0x00000914
|
|
#define I2S_OUT_CTL 0x00000918
|
|
#define AUTOCONFIG_REG 0x000009C4
|
|
|
|
/* Audio ADC Registers */
|
|
#define DSM_CTRL1 0x00000000
|
|
#define DSM_CTRL2 0x00000001
|
|
#define CHP_EN_CTRL 0x00000002
|
|
#define CHP_CLK_CTRL1 0x00000004
|
|
#define CHP_CLK_CTRL2 0x00000005
|
|
#define BG_REF_CTRL 0x00000006
|
|
#define SD2_SW_CTRL1 0x00000008
|
|
#define SD2_SW_CTRL2 0x00000009
|
|
#define SD2_BIAS_CTRL 0x0000000A
|
|
#define AMP_BIAS_CTRL 0x0000000C
|
|
#define CH_PWR_CTRL1 0x0000000E
|
|
#define FLD_CH_SEL (1 << 3)
|
|
#define CH_PWR_CTRL2 0x0000000F
|
|
#define DSM_STATUS1 0x00000010
|
|
#define DSM_STATUS2 0x00000011
|
|
#define DIG_CTL1 0x00000012
|
|
#define DIG_CTL2 0x00000013
|
|
#define I2S_TX_CFG 0x0000001A
|
|
|
|
#define DEV_CNTRL2 0x00040000
|
|
|
|
#define PCI_MSK_IR (1 << 28)
|
|
#define PCI_MSK_AV_CORE (1 << 27)
|
|
#define PCI_MSK_GPIO1 (1 << 24)
|
|
#define PCI_MSK_GPIO0 (1 << 23)
|
|
#define PCI_MSK_APB_DMA (1 << 12)
|
|
#define PCI_MSK_AL_WR (1 << 11)
|
|
#define PCI_MSK_AL_RD (1 << 10)
|
|
#define PCI_MSK_RISC_WR (1 << 9)
|
|
#define PCI_MSK_RISC_RD (1 << 8)
|
|
#define PCI_MSK_AUD_EXT (1 << 4)
|
|
#define PCI_MSK_AUD_INT (1 << 3)
|
|
#define PCI_MSK_VID_C (1 << 2)
|
|
#define PCI_MSK_VID_B (1 << 1)
|
|
#define PCI_MSK_VID_A 1
|
|
#define PCI_INT_MSK 0x00040010
|
|
|
|
#define PCI_INT_STAT 0x00040014
|
|
#define PCI_INT_MSTAT 0x00040018
|
|
|
|
#define VID_A_INT_MSK 0x00040020
|
|
#define VID_A_INT_STAT 0x00040024
|
|
#define VID_A_INT_MSTAT 0x00040028
|
|
#define VID_A_INT_SSTAT 0x0004002C
|
|
|
|
#define VID_B_INT_MSK 0x00040030
|
|
#define VID_B_MSK_BAD_PKT (1 << 20)
|
|
#define VID_B_MSK_VBI_OPC_ERR (1 << 17)
|
|
#define VID_B_MSK_OPC_ERR (1 << 16)
|
|
#define VID_B_MSK_VBI_SYNC (1 << 13)
|
|
#define VID_B_MSK_SYNC (1 << 12)
|
|
#define VID_B_MSK_VBI_OF (1 << 9)
|
|
#define VID_B_MSK_OF (1 << 8)
|
|
#define VID_B_MSK_VBI_RISCI2 (1 << 5)
|
|
#define VID_B_MSK_RISCI2 (1 << 4)
|
|
#define VID_B_MSK_VBI_RISCI1 (1 << 1)
|
|
#define VID_B_MSK_RISCI1 1
|
|
#define VID_B_INT_STAT 0x00040034
|
|
#define VID_B_INT_MSTAT 0x00040038
|
|
#define VID_B_INT_SSTAT 0x0004003C
|
|
|
|
#define VID_B_MSK_BAD_PKT (1 << 20)
|
|
#define VID_B_MSK_OPC_ERR (1 << 16)
|
|
#define VID_B_MSK_SYNC (1 << 12)
|
|
#define VID_B_MSK_OF (1 << 8)
|
|
#define VID_B_MSK_RISCI2 (1 << 4)
|
|
#define VID_B_MSK_RISCI1 1
|
|
|
|
#define VID_C_MSK_BAD_PKT (1 << 20)
|
|
#define VID_C_MSK_OPC_ERR (1 << 16)
|
|
#define VID_C_MSK_SYNC (1 << 12)
|
|
#define VID_C_MSK_OF (1 << 8)
|
|
#define VID_C_MSK_RISCI2 (1 << 4)
|
|
#define VID_C_MSK_RISCI1 1
|
|
|
|
/* A superset for testing purposes */
|
|
#define VID_BC_MSK_BAD_PKT (1 << 20)
|
|
#define VID_BC_MSK_OPC_ERR (1 << 16)
|
|
#define VID_BC_MSK_SYNC (1 << 12)
|
|
#define VID_BC_MSK_OF (1 << 8)
|
|
#define VID_BC_MSK_VBI_RISCI2 (1 << 5)
|
|
#define VID_BC_MSK_RISCI2 (1 << 4)
|
|
#define VID_BC_MSK_VBI_RISCI1 (1 << 1)
|
|
#define VID_BC_MSK_RISCI1 1
|
|
|
|
#define VID_C_INT_MSK 0x00040040
|
|
#define VID_C_INT_STAT 0x00040044
|
|
#define VID_C_INT_MSTAT 0x00040048
|
|
#define VID_C_INT_SSTAT 0x0004004C
|
|
|
|
#define AUDIO_INT_INT_MSK 0x00040050
|
|
#define AUDIO_INT_INT_STAT 0x00040054
|
|
#define AUDIO_INT_INT_MSTAT 0x00040058
|
|
#define AUDIO_INT_INT_SSTAT 0x0004005C
|
|
|
|
#define AUDIO_EXT_INT_MSK 0x00040060
|
|
#define AUDIO_EXT_INT_STAT 0x00040064
|
|
#define AUDIO_EXT_INT_MSTAT 0x00040068
|
|
#define AUDIO_EXT_INT_SSTAT 0x0004006C
|
|
|
|
/* Bits [7:0] set in both TC_REQ and TC_REQ_SET
|
|
* indicate a stall in the RISC engine for a
|
|
* particular rider traffic class. This causes
|
|
* the 885 and 888 bridges (unknown about 887)
|
|
* to become inoperable. Setting bits in
|
|
* TC_REQ_SET resets the corresponding bits
|
|
* in TC_REQ (and TC_REQ_SET) allowing
|
|
* operation to continue.
|
|
*/
|
|
#define TC_REQ 0x00040090
|
|
#define TC_REQ_SET 0x00040094
|
|
|
|
#define RDR_CFG0 0x00050000
|
|
#define RDR_CFG1 0x00050004
|
|
#define RDR_CFG2 0x00050008
|
|
#define RDR_RDRCTL1 0x0005030c
|
|
#define RDR_TLCTL0 0x00050318
|
|
|
|
/* APB DMAC Current Buffer Pointer */
|
|
#define DMA1_PTR1 0x00100000
|
|
#define DMA2_PTR1 0x00100004
|
|
#define DMA3_PTR1 0x00100008
|
|
#define DMA4_PTR1 0x0010000C
|
|
#define DMA5_PTR1 0x00100010
|
|
#define DMA6_PTR1 0x00100014
|
|
#define DMA7_PTR1 0x00100018
|
|
#define DMA8_PTR1 0x0010001C
|
|
|
|
/* APB DMAC Current Table Pointer */
|
|
#define DMA1_PTR2 0x00100040
|
|
#define DMA2_PTR2 0x00100044
|
|
#define DMA3_PTR2 0x00100048
|
|
#define DMA4_PTR2 0x0010004C
|
|
#define DMA5_PTR2 0x00100050
|
|
#define DMA6_PTR2 0x00100054
|
|
#define DMA7_PTR2 0x00100058
|
|
#define DMA8_PTR2 0x0010005C
|
|
|
|
/* APB DMAC Buffer Limit */
|
|
#define DMA1_CNT1 0x00100080
|
|
#define DMA2_CNT1 0x00100084
|
|
#define DMA3_CNT1 0x00100088
|
|
#define DMA4_CNT1 0x0010008C
|
|
#define DMA5_CNT1 0x00100090
|
|
#define DMA6_CNT1 0x00100094
|
|
#define DMA7_CNT1 0x00100098
|
|
#define DMA8_CNT1 0x0010009C
|
|
|
|
/* APB DMAC Table Size */
|
|
#define DMA1_CNT2 0x001000C0
|
|
#define DMA2_CNT2 0x001000C4
|
|
#define DMA3_CNT2 0x001000C8
|
|
#define DMA4_CNT2 0x001000CC
|
|
#define DMA5_CNT2 0x001000D0
|
|
#define DMA6_CNT2 0x001000D4
|
|
#define DMA7_CNT2 0x001000D8
|
|
#define DMA8_CNT2 0x001000DC
|
|
|
|
/* Timer Counters */
|
|
#define TM_CNT_LDW 0x00110000
|
|
#define TM_CNT_UW 0x00110004
|
|
#define TM_LMT_LDW 0x00110008
|
|
#define TM_LMT_UW 0x0011000C
|
|
|
|
/* GPIO */
|
|
#define GP0_IO 0x00110010
|
|
#define GPIO_ISM 0x00110014
|
|
#define SOFT_RESET 0x0011001C
|
|
|
|
/* GPIO (417 Microsoftcontroller) RW Data */
|
|
#define MC417_RWD 0x00110020
|
|
|
|
/* GPIO (417 Microsoftcontroller) Output Enable, Low Active */
|
|
#define MC417_OEN 0x00110024
|
|
#define MC417_CTL 0x00110028
|
|
#define ALT_PIN_OUT_SEL 0x0011002C
|
|
#define CLK_DELAY 0x00110048
|
|
#define PAD_CTRL 0x0011004C
|
|
|
|
/* Video A Interface */
|
|
#define VID_A_GPCNT 0x00130020
|
|
#define VBI_A_GPCNT 0x00130024
|
|
#define VID_A_GPCNT_CTL 0x00130030
|
|
#define VBI_A_GPCNT_CTL 0x00130034
|
|
#define VID_A_DMA_CTL 0x00130040
|
|
#define VID_A_VIP_CTRL 0x00130080
|
|
#define VID_A_PIXEL_FRMT 0x00130084
|
|
#define VID_A_VBI_CTRL 0x00130088
|
|
|
|
/* Video B Interface */
|
|
#define VID_B_DMA 0x00130100
|
|
#define VBI_B_DMA 0x00130108
|
|
#define VID_B_GPCNT 0x00130120
|
|
#define VBI_B_GPCNT 0x00130124
|
|
#define VID_B_GPCNT_CTL 0x00130134
|
|
#define VBI_B_GPCNT_CTL 0x00130138
|
|
#define VID_B_DMA_CTL 0x00130140
|
|
#define VID_B_SRC_SEL 0x00130144
|
|
#define VID_B_LNGTH 0x00130150
|
|
#define VID_B_HW_SOP_CTL 0x00130154
|
|
#define VID_B_GEN_CTL 0x00130158
|
|
#define VID_B_BD_PKT_STATUS 0x0013015C
|
|
#define VID_B_SOP_STATUS 0x00130160
|
|
#define VID_B_FIFO_OVFL_STAT 0x00130164
|
|
#define VID_B_VLD_MISC 0x00130168
|
|
#define VID_B_TS_CLK_EN 0x0013016C
|
|
#define VID_B_VIP_CTRL 0x00130180
|
|
#define VID_B_PIXEL_FRMT 0x00130184
|
|
|
|
/* Video C Interface */
|
|
#define VID_C_DMA 0x00130200
|
|
#define VBI_C_DMA 0x00130208
|
|
#define VID_C_GPCNT 0x00130220
|
|
#define VID_C_GPCNT_CTL 0x00130230
|
|
#define VBI_C_GPCNT_CTL 0x00130234
|
|
#define VID_C_DMA_CTL 0x00130240
|
|
#define VID_C_LNGTH 0x00130250
|
|
#define VID_C_HW_SOP_CTL 0x00130254
|
|
#define VID_C_GEN_CTL 0x00130258
|
|
#define VID_C_BD_PKT_STATUS 0x0013025C
|
|
#define VID_C_SOP_STATUS 0x00130260
|
|
#define VID_C_FIFO_OVFL_STAT 0x00130264
|
|
#define VID_C_VLD_MISC 0x00130268
|
|
#define VID_C_TS_CLK_EN 0x0013026C
|
|
|
|
/* Internal Audio Interface */
|
|
#define AUD_INT_A_GPCNT 0x00140020
|
|
#define AUD_INT_B_GPCNT 0x00140024
|
|
#define AUD_INT_A_GPCNT_CTL 0x00140030
|
|
#define AUD_INT_B_GPCNT_CTL 0x00140034
|
|
#define AUD_INT_DMA_CTL 0x00140040
|
|
#define AUD_INT_A_LNGTH 0x00140050
|
|
#define AUD_INT_B_LNGTH 0x00140054
|
|
#define AUD_INT_A_MODE 0x00140058
|
|
#define AUD_INT_B_MODE 0x0014005C
|
|
|
|
/* External Audio Interface */
|
|
#define AUD_EXT_DMA 0x00140100
|
|
#define AUD_EXT_GPCNT 0x00140120
|
|
#define AUD_EXT_GPCNT_CTL 0x00140130
|
|
#define AUD_EXT_DMA_CTL 0x00140140
|
|
#define AUD_EXT_LNGTH 0x00140150
|
|
#define AUD_EXT_A_MODE 0x00140158
|
|
|
|
/* I2C Bus 1 */
|
|
#define I2C1_ADDR 0x00180000
|
|
#define I2C1_WDATA 0x00180004
|
|
#define I2C1_CTRL 0x00180008
|
|
#define I2C1_RDATA 0x0018000C
|
|
#define I2C1_STAT 0x00180010
|
|
|
|
/* I2C Bus 2 */
|
|
#define I2C2_ADDR 0x00190000
|
|
#define I2C2_WDATA 0x00190004
|
|
#define I2C2_CTRL 0x00190008
|
|
#define I2C2_RDATA 0x0019000C
|
|
#define I2C2_STAT 0x00190010
|
|
|
|
/* I2C Bus 3 */
|
|
#define I2C3_ADDR 0x001A0000
|
|
#define I2C3_WDATA 0x001A0004
|
|
#define I2C3_CTRL 0x001A0008
|
|
#define I2C3_RDATA 0x001A000C
|
|
#define I2C3_STAT 0x001A0010
|
|
|
|
/* UART */
|
|
#define UART_CTL 0x001B0000
|
|
#define UART_BRD 0x001B0004
|
|
#define UART_ISR 0x001B000C
|
|
#define UART_CNT 0x001B0010
|
|
|
|
#endif /* _CX23885_REG_H_ */
|