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The AM572x Technical Reference Manual, SPRUHZ6H, Revised November 2016 [1], shows recommended settings for the SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings. Use those settings in the driver. The TRM does not show a value for 20MHz SYS_CLK so we use something close to the 26MHz setting. [1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf Signed-off-by: Roger Quadros <rogerq@ti.com> [nsekhar@ti.com: add exact TRM version to commit text] Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> |
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allwinner | ||
amlogic | ||
broadcom | ||
hisilicon | ||
marvell | ||
motorola | ||
qualcomm | ||
renesas | ||
rockchip | ||
samsung | ||
st | ||
tegra | ||
ti | ||
Kconfig | ||
Makefile | ||
phy-core.c | ||
phy-lpc18xx-usb-otg.c | ||
phy-mt65xx-usb3.c | ||
phy-pistachio-usb.c | ||
phy-xgene.c |