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49f3fbc7b8
The pm-mmp2 and pm-pxa910 power management related irq_set_wake callbacks fiddle pointlessly with the irq actions for no reason except for lack of understanding how the wakeup mechanism works. On supsend the core disables all interrupts lazily, i.e. it does not mask them at the irq controller level. So any interrupt which is firing during suspend will mark the corresponding interrupt line as pending. Just before the core powers down it checks whether there are interrupts pending from interrupt lines which are marked as wakeup sources and if so it aborts the suspend and resends the interrupts. If there was no interrupt at this point, the cpu goes into suspend with these interrupts unmasked. The IRQF_NO_SUSPEND flag for interrupt actions is a totally different mechanism. That allows the device driver to prevent the core from disabling the interrupt despite the fact that it is not marked as a wakeup source. This has nothing to do with the case at hand. It was introduced for special cases where lazy disable is not possible. Remove the nonsense along with the braindamaged boundary check. The core code does NOT call these functions out of boundary. Add a FIXME comment to an unhandled error path which merily printks some useless blurb instead of returning a proper error code. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: arm <linux-arm-kernel@lists.infradead.org> Cc: Eric Miao <eric.y.miao@gmail.com> Cc: Haojian Zhuang <haojian.zhuang@gmail.com> Cc: Russell King <linux@arm.linux.org.uk> Link: http://lkml.kernel.org/r/20140223212737.214342433@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
250 lines
5.8 KiB
C
250 lines
5.8 KiB
C
/*
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* MMP2 Power Management Routines
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*
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* This software program is licensed subject to the GNU General Public License
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* (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
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*
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* (C) Copyright 2012 Marvell International Ltd.
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* All Rights Reserved
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/time.h>
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#include <linux/delay.h>
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#include <linux/suspend.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <asm/mach-types.h>
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#include <mach/hardware.h>
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#include <mach/cputype.h>
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#include <mach/addr-map.h>
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#include <mach/pm-mmp2.h>
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#include <mach/regs-icu.h>
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#include <mach/irqs.h>
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int mmp2_set_wake(struct irq_data *d, unsigned int on)
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{
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unsigned long data = 0;
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int irq = d->irq;
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/* enable wakeup sources */
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switch (irq) {
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case IRQ_MMP2_RTC:
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case IRQ_MMP2_RTC_ALARM:
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data = MPMU_WUCRM_PJ_WAKEUP(4) | MPMU_WUCRM_PJ_RTC_ALARM;
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break;
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case IRQ_MMP2_PMIC:
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data = MPMU_WUCRM_PJ_WAKEUP(7);
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break;
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case IRQ_MMP2_MMC2:
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/* mmc use WAKEUP2, same as GPIO wakeup source */
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data = MPMU_WUCRM_PJ_WAKEUP(2);
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break;
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}
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if (on) {
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if (data) {
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data |= __raw_readl(MPMU_WUCRM_PJ);
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__raw_writel(data, MPMU_WUCRM_PJ);
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}
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} else {
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if (data) {
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data = ~data & __raw_readl(MPMU_WUCRM_PJ);
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__raw_writel(data, MPMU_WUCRM_PJ);
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}
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}
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return 0;
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}
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static void pm_scu_clk_disable(void)
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{
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unsigned int val;
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/* close AXI fabric clock gate */
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__raw_writel(0x0, CIU_REG(0x64));
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__raw_writel(0x0, CIU_REG(0x68));
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/* close MCB master clock gate */
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val = __raw_readl(CIU_REG(0x1c));
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val |= 0xf0;
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__raw_writel(val, CIU_REG(0x1c));
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return ;
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}
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static void pm_scu_clk_enable(void)
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{
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unsigned int val;
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/* open AXI fabric clock gate */
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__raw_writel(0x03003003, CIU_REG(0x64));
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__raw_writel(0x00303030, CIU_REG(0x68));
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/* open MCB master clock gate */
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val = __raw_readl(CIU_REG(0x1c));
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val &= ~(0xf0);
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__raw_writel(val, CIU_REG(0x1c));
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return ;
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}
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static void pm_mpmu_clk_disable(void)
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{
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/*
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* disable clocks in MPMU_CGR_PJ register
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* except clock for APMU_PLL1, APMU_PLL1_2 and AP_26M
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*/
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__raw_writel(0x0000a010, MPMU_CGR_PJ);
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}
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static void pm_mpmu_clk_enable(void)
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{
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unsigned int val;
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__raw_writel(0xdffefffe, MPMU_CGR_PJ);
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val = __raw_readl(MPMU_PLL2_CTRL1);
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val |= (1 << 29);
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__raw_writel(val, MPMU_PLL2_CTRL1);
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return ;
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}
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void mmp2_pm_enter_lowpower_mode(int state)
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{
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uint32_t idle_cfg, apcr;
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idle_cfg = __raw_readl(APMU_PJ_IDLE_CFG);
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apcr = __raw_readl(MPMU_PCR_PJ);
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apcr &= ~(MPMU_PCR_PJ_SLPEN | MPMU_PCR_PJ_DDRCORSD | MPMU_PCR_PJ_APBSD
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| MPMU_PCR_PJ_AXISD | MPMU_PCR_PJ_VCTCXOSD | (1 << 13));
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idle_cfg &= ~APMU_PJ_IDLE_CFG_PJ_IDLE;
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switch (state) {
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case POWER_MODE_SYS_SLEEP:
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apcr |= MPMU_PCR_PJ_SLPEN; /* set the SLPEN bit */
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apcr |= MPMU_PCR_PJ_VCTCXOSD; /* set VCTCXOSD */
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/* fall through */
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case POWER_MODE_CHIP_SLEEP:
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apcr |= MPMU_PCR_PJ_SLPEN;
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/* fall through */
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case POWER_MODE_APPS_SLEEP:
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apcr |= MPMU_PCR_PJ_APBSD; /* set APBSD */
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/* fall through */
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case POWER_MODE_APPS_IDLE:
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apcr |= MPMU_PCR_PJ_AXISD; /* set AXISDD bit */
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apcr |= MPMU_PCR_PJ_DDRCORSD; /* set DDRCORSD bit */
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idle_cfg |= APMU_PJ_IDLE_CFG_PJ_PWRDWN; /* PJ power down */
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apcr |= MPMU_PCR_PJ_SPSD;
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/* fall through */
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case POWER_MODE_CORE_EXTIDLE:
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idle_cfg |= APMU_PJ_IDLE_CFG_PJ_IDLE; /* set the IDLE bit */
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idle_cfg &= ~APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK;
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idle_cfg |= APMU_PJ_IDLE_CFG_PWR_SW(3)
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| APMU_PJ_IDLE_CFG_L2_PWR_SW;
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break;
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case POWER_MODE_CORE_INTIDLE:
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apcr &= ~MPMU_PCR_PJ_SPSD;
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break;
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}
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/* set reserve bits */
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apcr |= (1 << 30) | (1 << 25);
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/* finally write the registers back */
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__raw_writel(idle_cfg, APMU_PJ_IDLE_CFG);
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__raw_writel(apcr, MPMU_PCR_PJ); /* 0xfe086000 */
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}
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static int mmp2_pm_enter(suspend_state_t state)
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{
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int temp;
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temp = __raw_readl(MMP2_ICU_INT4_MASK);
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if (temp & (1 << 1)) {
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printk(KERN_ERR "%s: PMIC interrupt is handling\n", __func__);
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return -EAGAIN;
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}
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temp = __raw_readl(APMU_SRAM_PWR_DWN);
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temp |= ((1 << 19) | (1 << 18));
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__raw_writel(temp, APMU_SRAM_PWR_DWN);
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pm_mpmu_clk_disable();
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pm_scu_clk_disable();
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printk(KERN_INFO "%s: before suspend\n", __func__);
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cpu_do_idle();
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printk(KERN_INFO "%s: after suspend\n", __func__);
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pm_mpmu_clk_enable(); /* enable clocks in MPMU */
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pm_scu_clk_enable(); /* enable clocks in SCU */
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return 0;
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}
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/*
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* Called after processes are frozen, but before we shut down devices.
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*/
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static int mmp2_pm_prepare(void)
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{
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mmp2_pm_enter_lowpower_mode(POWER_MODE_SYS_SLEEP);
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return 0;
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}
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/*
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* Called after devices are re-setup, but before processes are thawed.
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*/
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static void mmp2_pm_finish(void)
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{
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mmp2_pm_enter_lowpower_mode(POWER_MODE_CORE_INTIDLE);
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}
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static int mmp2_pm_valid(suspend_state_t state)
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{
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return ((state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM));
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}
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/*
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* Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
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*/
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static const struct platform_suspend_ops mmp2_pm_ops = {
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.valid = mmp2_pm_valid,
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.prepare = mmp2_pm_prepare,
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.enter = mmp2_pm_enter,
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.finish = mmp2_pm_finish,
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};
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static int __init mmp2_pm_init(void)
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{
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uint32_t apcr;
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if (!cpu_is_mmp2())
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return -EIO;
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suspend_set_ops(&mmp2_pm_ops);
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/*
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* Set bit 0, Slow clock Select 32K clock input instead of VCXO
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* VCXO is chosen by default, which would be disabled in suspend
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*/
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__raw_writel(0x5, MPMU_SCCR);
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/*
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* Clear bit 23 of CIU_CPU_CONF
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* direct PJ4 to DDR access through Memory Controller slow queue
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* fast queue has issue and cause lcd will flick
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*/
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__raw_writel(__raw_readl(CIU_REG(0x8)) & ~(0x1 << 23), CIU_REG(0x8));
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/* Clear default low power control bit */
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apcr = __raw_readl(MPMU_PCR_PJ);
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apcr &= ~(MPMU_PCR_PJ_SLPEN | MPMU_PCR_PJ_DDRCORSD
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| MPMU_PCR_PJ_APBSD | MPMU_PCR_PJ_AXISD | 1 << 13);
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__raw_writel(apcr, MPMU_PCR_PJ);
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return 0;
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}
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late_initcall(mmp2_pm_init);
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