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311c7c71c9
By affinity hints and XPS, each mlx5e channel is assigned a CPU core. Channel DMA coherent memory that is written by the NIC and read by SW (e.g CQ buffer) is allocated on the NUMA node of the CPU core assigned for the channel. Channel DMA coherent memory that is written by SW and read by the NIC (e.g SQ/RQ buffer) is allocated on the NUMA node of the NIC. Doorbell record (written by SW and read by the NIC) is an exception since it is accessed by SW more frequently. Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: Amir Vadai <amirv@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
172 lines
4.3 KiB
C
172 lines
4.3 KiB
C
/*
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* Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __MLX5_WQ_H__
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#define __MLX5_WQ_H__
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#include <linux/mlx5/mlx5_ifc.h>
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struct mlx5_wq_param {
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int linear;
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int buf_numa_node;
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int db_numa_node;
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};
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struct mlx5_wq_ctrl {
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struct mlx5_core_dev *mdev;
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struct mlx5_buf buf;
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struct mlx5_db db;
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};
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struct mlx5_wq_cyc {
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void *buf;
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__be32 *db;
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u16 sz_m1;
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u8 log_stride;
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};
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struct mlx5_cqwq {
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void *buf;
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__be32 *db;
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u32 sz_m1;
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u32 cc; /* consumer counter */
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u8 log_sz;
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u8 log_stride;
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};
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struct mlx5_wq_ll {
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void *buf;
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__be32 *db;
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__be16 *tail_next;
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u16 sz_m1;
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u16 head;
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u16 wqe_ctr;
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u16 cur_sz;
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u8 log_stride;
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};
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int mlx5_wq_cyc_create(struct mlx5_core_dev *mdev, struct mlx5_wq_param *param,
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void *wqc, struct mlx5_wq_cyc *wq,
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struct mlx5_wq_ctrl *wq_ctrl);
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u32 mlx5_wq_cyc_get_size(struct mlx5_wq_cyc *wq);
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int mlx5_cqwq_create(struct mlx5_core_dev *mdev, struct mlx5_wq_param *param,
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void *cqc, struct mlx5_cqwq *wq,
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struct mlx5_wq_ctrl *wq_ctrl);
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u32 mlx5_cqwq_get_size(struct mlx5_cqwq *wq);
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int mlx5_wq_ll_create(struct mlx5_core_dev *mdev, struct mlx5_wq_param *param,
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void *wqc, struct mlx5_wq_ll *wq,
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struct mlx5_wq_ctrl *wq_ctrl);
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u32 mlx5_wq_ll_get_size(struct mlx5_wq_ll *wq);
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void mlx5_wq_destroy(struct mlx5_wq_ctrl *wq_ctrl);
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static inline u16 mlx5_wq_cyc_ctr2ix(struct mlx5_wq_cyc *wq, u16 ctr)
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{
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return ctr & wq->sz_m1;
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}
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static inline void *mlx5_wq_cyc_get_wqe(struct mlx5_wq_cyc *wq, u16 ix)
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{
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return wq->buf + (ix << wq->log_stride);
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}
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static inline int mlx5_wq_cyc_cc_bigger(u16 cc1, u16 cc2)
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{
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int equal = (cc1 == cc2);
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int smaller = 0x8000 & (cc1 - cc2);
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return !equal && !smaller;
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}
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static inline u32 mlx5_cqwq_get_ci(struct mlx5_cqwq *wq)
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{
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return wq->cc & wq->sz_m1;
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}
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static inline void *mlx5_cqwq_get_wqe(struct mlx5_cqwq *wq, u32 ix)
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{
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return wq->buf + (ix << wq->log_stride);
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}
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static inline u32 mlx5_cqwq_get_wrap_cnt(struct mlx5_cqwq *wq)
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{
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return wq->cc >> wq->log_sz;
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}
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static inline void mlx5_cqwq_pop(struct mlx5_cqwq *wq)
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{
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wq->cc++;
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}
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static inline void mlx5_cqwq_update_db_record(struct mlx5_cqwq *wq)
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{
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*wq->db = cpu_to_be32(wq->cc & 0xffffff);
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}
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static inline int mlx5_wq_ll_is_full(struct mlx5_wq_ll *wq)
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{
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return wq->cur_sz == wq->sz_m1;
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}
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static inline int mlx5_wq_ll_is_empty(struct mlx5_wq_ll *wq)
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{
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return !wq->cur_sz;
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}
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static inline void *mlx5_wq_ll_get_wqe(struct mlx5_wq_ll *wq, u16 ix)
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{
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return wq->buf + (ix << wq->log_stride);
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}
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static inline void mlx5_wq_ll_push(struct mlx5_wq_ll *wq, u16 head_next)
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{
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wq->head = head_next;
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wq->wqe_ctr++;
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wq->cur_sz++;
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}
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static inline void mlx5_wq_ll_pop(struct mlx5_wq_ll *wq, __be16 ix,
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__be16 *next_tail_next)
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{
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*wq->tail_next = ix;
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wq->tail_next = next_tail_next;
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wq->cur_sz--;
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}
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static inline void mlx5_wq_ll_update_db_record(struct mlx5_wq_ll *wq)
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{
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*wq->db = cpu_to_be32(wq->wqe_ctr);
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}
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#endif /* __MLX5_WQ_H__ */
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