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![Michael Roth](/assets/img/avatar_default.png)
On a 2-socket Power9 system with 32 cores/128 threads (SMT4) and 1TB
of memory running the following guest configs:
guest A:
- 224GB of memory
- 56 VCPUs (sockets=1,cores=28,threads=2), where:
VCPUs 0-1 are pinned to CPUs 0-3,
VCPUs 2-3 are pinned to CPUs 4-7,
...
VCPUs 54-55 are pinned to CPUs 108-111
guest B:
- 4GB of memory
- 4 VCPUs (sockets=1,cores=4,threads=1)
with the following workloads (with KSM and THP enabled in all):
guest A:
stress --cpu 40 --io 20 --vm 20 --vm-bytes 512M
guest B:
stress --cpu 4 --io 4 --vm 4 --vm-bytes 512M
host:
stress --cpu 4 --io 4 --vm 2 --vm-bytes 256M
the below soft-lockup traces were observed after an hour or so and
persisted until the host was reset (this was found to be reliably
reproducible for this configuration, for kernels 4.15, 4.18, 5.0,
and 5.3-rc5):
[ 1253.183290] rcu: INFO: rcu_sched self-detected stall on CPU
[ 1253.183319] rcu: 124-....: (5250 ticks this GP) idle=10a/1/0x4000000000000002 softirq=5408/5408 fqs=1941
[ 1256.287426] watchdog: BUG: soft lockup - CPU#105 stuck for 23s! [CPU 52/KVM:19709]
[ 1264.075773] watchdog: BUG: soft lockup - CPU#24 stuck for 23s! [worker:19913]
[ 1264.079769] watchdog: BUG: soft lockup - CPU#31 stuck for 23s! [worker:20331]
[ 1264.095770] watchdog: BUG: soft lockup - CPU#45 stuck for 23s! [worker:20338]
[ 1264.131773] watchdog: BUG: soft lockup - CPU#64 stuck for 23s! [avocado:19525]
[ 1280.408480] watchdog: BUG: soft lockup - CPU#124 stuck for 22s! [ksmd:791]
[ 1316.198012] rcu: INFO: rcu_sched self-detected stall on CPU
[ 1316.198032] rcu: 124-....: (21003 ticks this GP) idle=10a/1/0x4000000000000002 softirq=5408/5408 fqs=8243
[ 1340.411024] watchdog: BUG: soft lockup - CPU#124 stuck for 22s! [ksmd:791]
[ 1379.212609] rcu: INFO: rcu_sched self-detected stall on CPU
[ 1379.212629] rcu: 124-....: (36756 ticks this GP) idle=10a/1/0x4000000000000002 softirq=5408/5408 fqs=14714
[ 1404.413615] watchdog: BUG: soft lockup - CPU#124 stuck for 22s! [ksmd:791]
[ 1442.227095] rcu: INFO: rcu_sched self-detected stall on CPU
[ 1442.227115] rcu: 124-....: (52509 ticks this GP) idle=10a/1/0x4000000000000002 softirq=5408/5408 fqs=21403
[ 1455.111787] INFO: task worker:19907 blocked for more than 120 seconds.
[ 1455.111822] Tainted: G L 5.3.0-rc5-mdr-vanilla+ #1
[ 1455.111833] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[ 1455.111884] INFO: task worker:19908 blocked for more than 120 seconds.
[ 1455.111905] Tainted: G L 5.3.0-rc5-mdr-vanilla+ #1
[ 1455.111925] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[ 1455.111966] INFO: task worker:20328 blocked for more than 120 seconds.
[ 1455.111986] Tainted: G L 5.3.0-rc5-mdr-vanilla+ #1
[ 1455.111998] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[ 1455.112048] INFO: task worker:20330 blocked for more than 120 seconds.
[ 1455.112068] Tainted: G L 5.3.0-rc5-mdr-vanilla+ #1
[ 1455.112097] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[ 1455.112138] INFO: task worker:20332 blocked for more than 120 seconds.
[ 1455.112159] Tainted: G L 5.3.0-rc5-mdr-vanilla+ #1
[ 1455.112179] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[ 1455.112210] INFO: task worker:20333 blocked for more than 120 seconds.
[ 1455.112231] Tainted: G L 5.3.0-rc5-mdr-vanilla+ #1
[ 1455.112242] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[ 1455.112282] INFO: task worker:20335 blocked for more than 120 seconds.
[ 1455.112303] Tainted: G L 5.3.0-rc5-mdr-vanilla+ #1
[ 1455.112332] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[ 1455.112372] INFO: task worker:20336 blocked for more than 120 seconds.
[ 1455.112392] Tainted: G L 5.3.0-rc5-mdr-vanilla+ #1
CPUs 45, 24, and 124 are stuck on spin locks, likely held by
CPUs 105 and 31.
CPUs 105 and 31 are stuck in smp_call_function_many(), waiting on
target CPU 42. For instance:
# CPU 105 registers (via xmon)
R00 = c00000000020b20c R16 = 00007d1bcd800000
R01 = c00000363eaa7970 R17 = 0000000000000001
R02 = c0000000019b3a00 R18 = 000000000000006b
R03 = 000000000000002a R19 = 00007d537d7aecf0
R04 = 000000000000002a R20 = 60000000000000e0
R05 = 000000000000002a R21 = 0801000000000080
R06 = c0002073fb0caa08 R22 = 0000000000000d60
R07 = c0000000019ddd78 R23 = 0000000000000001
R08 = 000000000000002a R24 = c00000000147a700
R09 = 0000000000000001 R25 = c0002073fb0ca908
R10 = c000008ffeb4e660 R26 = 0000000000000000
R11 = c0002073fb0ca900 R27 = c0000000019e2464
R12 = c000000000050790 R28 = c0000000000812b0
R13 = c000207fff623e00 R29 = c0002073fb0ca808
R14 = 00007d1bbee00000 R30 = c0002073fb0ca800
R15 = 00007d1bcd600000 R31 = 0000000000000800
pc = c00000000020b260 smp_call_function_many+0x3d0/0x460
cfar= c00000000020b270 smp_call_function_many+0x3e0/0x460
lr = c00000000020b20c smp_call_function_many+0x37c/0x460
msr = 900000010288b033 cr = 44024824
ctr = c000000000050790 xer = 0000000000000000 trap = 100
CPU 42 is running normally, doing VCPU work:
# CPU 42 stack trace (via xmon)
[link register ] c00800001be17188 kvmppc_book3s_radix_page_fault+0x90/0x2b0 [kvm_hv]
[c000008ed3343820] c000008ed3343850 (unreliable)
[c000008ed33438d0] c00800001be11b6c kvmppc_book3s_hv_page_fault+0x264/0xe30 [kvm_hv]
[c000008ed33439d0] c00800001be0d7b4 kvmppc_vcpu_run_hv+0x8dc/0xb50 [kvm_hv]
[c000008ed3343ae0] c00800001c10891c kvmppc_vcpu_run+0x34/0x48 [kvm]
[c000008ed3343b00] c00800001c10475c kvm_arch_vcpu_ioctl_run+0x244/0x420 [kvm]
[c000008ed3343b90] c00800001c0f5a78 kvm_vcpu_ioctl+0x470/0x7c8 [kvm]
[c000008ed3343d00] c000000000475450 do_vfs_ioctl+0xe0/0xc70
[c000008ed3343db0] c0000000004760e4 ksys_ioctl+0x104/0x120
[c000008ed3343e00] c000000000476128 sys_ioctl+0x28/0x80
[c000008ed3343e20] c00000000000b388 system_call+0x5c/0x70
--- Exception: c00 (System Call) at 00007d545cfd7694
SP (7d53ff7edf50) is in userspace
It was subsequently found that ipi_message[PPC_MSG_CALL_FUNCTION]
was set for CPU 42 by at least 1 of the CPUs waiting in
smp_call_function_many(), but somehow the corresponding
call_single_queue entries were never processed by CPU 42, causing the
callers to spin in csd_lock_wait() indefinitely.
Nick Piggin suggested something similar to the following sequence as
a possible explanation (interleaving of CALL_FUNCTION/RESCHEDULE
IPI messages seems to be most common, but any mix of CALL_FUNCTION and
!CALL_FUNCTION messages could trigger it):
CPU
X: smp_muxed_ipi_set_message():
X: smp_mb()
X: message[RESCHEDULE] = 1
X: doorbell_global_ipi(42):
X: kvmppc_set_host_ipi(42, 1)
X: ppc_msgsnd_sync()/smp_mb()
X: ppc_msgsnd() -> 42
42: doorbell_exception(): // from CPU X
42: ppc_msgsync()
105: smp_muxed_ipi_set_message():
105: smb_mb()
// STORE DEFERRED DUE TO RE-ORDERING
--105: message[CALL_FUNCTION] = 1
| 105: doorbell_global_ipi(42):
| 105: kvmppc_set_host_ipi(42, 1)
| 42: kvmppc_set_host_ipi(42, 0)
| 42: smp_ipi_demux_relaxed()
| 42: // returns to executing guest
| // RE-ORDERED STORE COMPLETES
->105: message[CALL_FUNCTION] = 1
105: ppc_msgsnd_sync()/smp_mb()
105: ppc_msgsnd() -> 42
42: local_paca->kvm_hstate.host_ipi == 0 // IPI ignored
105: // hangs waiting on 42 to process messages/call_single_queue
This can be prevented with an smp_mb() at the beginning of
kvmppc_set_host_ipi(), such that stores to message[<type>] (or other
state indicated by the host_ipi flag) are ordered vs. the store to
to host_ipi.
However, doing so might still allow for the following scenario (not
yet observed):
CPU
X: smp_muxed_ipi_set_message():
X: smp_mb()
X: message[RESCHEDULE] = 1
X: doorbell_global_ipi(42):
X: kvmppc_set_host_ipi(42, 1)
X: ppc_msgsnd_sync()/smp_mb()
X: ppc_msgsnd() -> 42
42: doorbell_exception(): // from CPU X
42: ppc_msgsync()
// STORE DEFERRED DUE TO RE-ORDERING
-- 42: kvmppc_set_host_ipi(42, 0)
| 42: smp_ipi_demux_relaxed()
| 105: smp_muxed_ipi_set_message():
| 105: smb_mb()
| 105: message[CALL_FUNCTION] = 1
| 105: doorbell_global_ipi(42):
| 105: kvmppc_set_host_ipi(42, 1)
| // RE-ORDERED STORE COMPLETES
-> 42: kvmppc_set_host_ipi(42, 0)
42: // returns to executing guest
105: ppc_msgsnd_sync()/smp_mb()
105: ppc_msgsnd() -> 42
42: local_paca->kvm_hstate.host_ipi == 0 // IPI ignored
105: // hangs waiting on 42 to process messages/call_single_queue
Fixing this scenario would require an smp_mb() *after* clearing
host_ipi flag in kvmppc_set_host_ipi() to order the store vs.
subsequent processing of IPI messages.
To handle both cases, this patch splits kvmppc_set_host_ipi() into
separate set/clear functions, where we execute smp_mb() prior to
setting host_ipi flag, and after clearing host_ipi flag. These
functions pair with each other to synchronize the sender and receiver
sides.
With that change in place the above workload ran for 20 hours without
triggering any lock-ups.
Fixes: 755563bc79
("powerpc/powernv: Fixes for hypervisor doorbell handling") # v4.0
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
Acked-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20190911223155.16045-1-mdroth@linux.vnet.ibm.com
934 lines
24 KiB
C
934 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright 2012 Michael Ellerman, IBM Corporation.
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* Copyright 2012 Benjamin Herrenschmidt, IBM Corporation
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*/
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#include <linux/kernel.h>
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#include <linux/kvm_host.h>
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#include <linux/err.h>
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#include <linux/kernel_stat.h>
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#include <asm/kvm_book3s.h>
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#include <asm/kvm_ppc.h>
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#include <asm/hvcall.h>
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#include <asm/xics.h>
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#include <asm/synch.h>
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#include <asm/cputhreads.h>
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#include <asm/pgtable.h>
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#include <asm/ppc-opcode.h>
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#include <asm/pnv-pci.h>
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#include <asm/opal.h>
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#include <asm/smp.h>
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#include "book3s_xics.h"
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#define DEBUG_PASSUP
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int h_ipi_redirect = 1;
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EXPORT_SYMBOL(h_ipi_redirect);
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int kvm_irq_bypass = 1;
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EXPORT_SYMBOL(kvm_irq_bypass);
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static void icp_rm_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
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u32 new_irq, bool check_resend);
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static int xics_opal_set_server(unsigned int hw_irq, int server_cpu);
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/* -- ICS routines -- */
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static void ics_rm_check_resend(struct kvmppc_xics *xics,
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struct kvmppc_ics *ics, struct kvmppc_icp *icp)
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{
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int i;
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for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) {
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struct ics_irq_state *state = &ics->irq_state[i];
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if (state->resend)
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icp_rm_deliver_irq(xics, icp, state->number, true);
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}
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}
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/* -- ICP routines -- */
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#ifdef CONFIG_SMP
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static inline void icp_send_hcore_msg(int hcore, struct kvm_vcpu *vcpu)
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{
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int hcpu;
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hcpu = hcore << threads_shift;
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kvmppc_host_rm_ops_hv->rm_core[hcore].rm_data = vcpu;
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smp_muxed_ipi_set_message(hcpu, PPC_MSG_RM_HOST_ACTION);
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kvmppc_set_host_ipi(hcpu);
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smp_mb();
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kvmhv_rm_send_ipi(hcpu);
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}
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#else
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static inline void icp_send_hcore_msg(int hcore, struct kvm_vcpu *vcpu) { }
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#endif
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/*
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* We start the search from our current CPU Id in the core map
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* and go in a circle until we get back to our ID looking for a
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* core that is running in host context and that hasn't already
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* been targeted for another rm_host_ops.
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*
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* In the future, could consider using a fairer algorithm (one
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* that distributes the IPIs better)
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*
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* Returns -1, if no CPU could be found in the host
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* Else, returns a CPU Id which has been reserved for use
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*/
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static inline int grab_next_hostcore(int start,
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struct kvmppc_host_rm_core *rm_core, int max, int action)
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{
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bool success;
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int core;
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union kvmppc_rm_state old, new;
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for (core = start + 1; core < max; core++) {
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old = new = READ_ONCE(rm_core[core].rm_state);
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if (!old.in_host || old.rm_action)
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continue;
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/* Try to grab this host core if not taken already. */
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new.rm_action = action;
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success = cmpxchg64(&rm_core[core].rm_state.raw,
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old.raw, new.raw) == old.raw;
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if (success) {
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/*
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* Make sure that the store to the rm_action is made
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* visible before we return to caller (and the
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* subsequent store to rm_data) to synchronize with
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* the IPI handler.
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*/
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smp_wmb();
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return core;
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}
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}
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return -1;
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}
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static inline int find_available_hostcore(int action)
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{
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int core;
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int my_core = smp_processor_id() >> threads_shift;
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struct kvmppc_host_rm_core *rm_core = kvmppc_host_rm_ops_hv->rm_core;
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core = grab_next_hostcore(my_core, rm_core, cpu_nr_cores(), action);
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if (core == -1)
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core = grab_next_hostcore(core, rm_core, my_core, action);
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return core;
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}
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static void icp_rm_set_vcpu_irq(struct kvm_vcpu *vcpu,
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struct kvm_vcpu *this_vcpu)
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{
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struct kvmppc_icp *this_icp = this_vcpu->arch.icp;
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int cpu;
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int hcore;
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/* Mark the target VCPU as having an interrupt pending */
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vcpu->stat.queue_intr++;
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set_bit(BOOK3S_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions);
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/* Kick self ? Just set MER and return */
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if (vcpu == this_vcpu) {
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mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_MER);
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return;
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}
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if (xive_enabled() && kvmhv_on_pseries()) {
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/* No XICS access or hypercalls available, too hard */
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this_icp->rm_action |= XICS_RM_KICK_VCPU;
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this_icp->rm_kick_target = vcpu;
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return;
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}
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/*
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* Check if the core is loaded,
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* if not, find an available host core to post to wake the VCPU,
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* if we can't find one, set up state to eventually return too hard.
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*/
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cpu = vcpu->arch.thread_cpu;
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if (cpu < 0 || cpu >= nr_cpu_ids) {
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hcore = -1;
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if (kvmppc_host_rm_ops_hv && h_ipi_redirect)
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hcore = find_available_hostcore(XICS_RM_KICK_VCPU);
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if (hcore != -1) {
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icp_send_hcore_msg(hcore, vcpu);
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} else {
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this_icp->rm_action |= XICS_RM_KICK_VCPU;
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this_icp->rm_kick_target = vcpu;
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}
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return;
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}
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smp_mb();
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kvmhv_rm_send_ipi(cpu);
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}
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static void icp_rm_clr_vcpu_irq(struct kvm_vcpu *vcpu)
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{
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/* Note: Only called on self ! */
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clear_bit(BOOK3S_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions);
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mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~LPCR_MER);
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}
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static inline bool icp_rm_try_update(struct kvmppc_icp *icp,
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union kvmppc_icp_state old,
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union kvmppc_icp_state new)
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{
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struct kvm_vcpu *this_vcpu = local_paca->kvm_hstate.kvm_vcpu;
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bool success;
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/* Calculate new output value */
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new.out_ee = (new.xisr && (new.pending_pri < new.cppr));
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/* Attempt atomic update */
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success = cmpxchg64(&icp->state.raw, old.raw, new.raw) == old.raw;
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if (!success)
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goto bail;
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/*
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* Check for output state update
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*
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* Note that this is racy since another processor could be updating
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* the state already. This is why we never clear the interrupt output
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* here, we only ever set it. The clear only happens prior to doing
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* an update and only by the processor itself. Currently we do it
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* in Accept (H_XIRR) and Up_Cppr (H_XPPR).
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*
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* We also do not try to figure out whether the EE state has changed,
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* we unconditionally set it if the new state calls for it. The reason
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* for that is that we opportunistically remove the pending interrupt
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* flag when raising CPPR, so we need to set it back here if an
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* interrupt is still pending.
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*/
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if (new.out_ee)
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icp_rm_set_vcpu_irq(icp->vcpu, this_vcpu);
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/* Expose the state change for debug purposes */
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this_vcpu->arch.icp->rm_dbgstate = new;
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this_vcpu->arch.icp->rm_dbgtgt = icp->vcpu;
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bail:
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return success;
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}
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static inline int check_too_hard(struct kvmppc_xics *xics,
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struct kvmppc_icp *icp)
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{
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return (xics->real_mode_dbg || icp->rm_action) ? H_TOO_HARD : H_SUCCESS;
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}
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static void icp_rm_check_resend(struct kvmppc_xics *xics,
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struct kvmppc_icp *icp)
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{
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u32 icsid;
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/* Order this load with the test for need_resend in the caller */
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smp_rmb();
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for_each_set_bit(icsid, icp->resend_map, xics->max_icsid + 1) {
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struct kvmppc_ics *ics = xics->ics[icsid];
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if (!test_and_clear_bit(icsid, icp->resend_map))
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continue;
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if (!ics)
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continue;
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ics_rm_check_resend(xics, ics, icp);
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}
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}
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static bool icp_rm_try_to_deliver(struct kvmppc_icp *icp, u32 irq, u8 priority,
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u32 *reject)
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{
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union kvmppc_icp_state old_state, new_state;
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bool success;
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do {
|
|
old_state = new_state = READ_ONCE(icp->state);
|
|
|
|
*reject = 0;
|
|
|
|
/* See if we can deliver */
|
|
success = new_state.cppr > priority &&
|
|
new_state.mfrr > priority &&
|
|
new_state.pending_pri > priority;
|
|
|
|
/*
|
|
* If we can, check for a rejection and perform the
|
|
* delivery
|
|
*/
|
|
if (success) {
|
|
*reject = new_state.xisr;
|
|
new_state.xisr = irq;
|
|
new_state.pending_pri = priority;
|
|
} else {
|
|
/*
|
|
* If we failed to deliver we set need_resend
|
|
* so a subsequent CPPR state change causes us
|
|
* to try a new delivery.
|
|
*/
|
|
new_state.need_resend = true;
|
|
}
|
|
|
|
} while (!icp_rm_try_update(icp, old_state, new_state));
|
|
|
|
return success;
|
|
}
|
|
|
|
static void icp_rm_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
|
|
u32 new_irq, bool check_resend)
|
|
{
|
|
struct ics_irq_state *state;
|
|
struct kvmppc_ics *ics;
|
|
u32 reject;
|
|
u16 src;
|
|
|
|
/*
|
|
* This is used both for initial delivery of an interrupt and
|
|
* for subsequent rejection.
|
|
*
|
|
* Rejection can be racy vs. resends. We have evaluated the
|
|
* rejection in an atomic ICP transaction which is now complete,
|
|
* so potentially the ICP can already accept the interrupt again.
|
|
*
|
|
* So we need to retry the delivery. Essentially the reject path
|
|
* boils down to a failed delivery. Always.
|
|
*
|
|
* Now the interrupt could also have moved to a different target,
|
|
* thus we may need to re-do the ICP lookup as well
|
|
*/
|
|
|
|
again:
|
|
/* Get the ICS state and lock it */
|
|
ics = kvmppc_xics_find_ics(xics, new_irq, &src);
|
|
if (!ics) {
|
|
/* Unsafe increment, but this does not need to be accurate */
|
|
xics->err_noics++;
|
|
return;
|
|
}
|
|
state = &ics->irq_state[src];
|
|
|
|
/* Get a lock on the ICS */
|
|
arch_spin_lock(&ics->lock);
|
|
|
|
/* Get our server */
|
|
if (!icp || state->server != icp->server_num) {
|
|
icp = kvmppc_xics_find_server(xics->kvm, state->server);
|
|
if (!icp) {
|
|
/* Unsafe increment again*/
|
|
xics->err_noicp++;
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
if (check_resend)
|
|
if (!state->resend)
|
|
goto out;
|
|
|
|
/* Clear the resend bit of that interrupt */
|
|
state->resend = 0;
|
|
|
|
/*
|
|
* If masked, bail out
|
|
*
|
|
* Note: PAPR doesn't mention anything about masked pending
|
|
* when doing a resend, only when doing a delivery.
|
|
*
|
|
* However that would have the effect of losing a masked
|
|
* interrupt that was rejected and isn't consistent with
|
|
* the whole masked_pending business which is about not
|
|
* losing interrupts that occur while masked.
|
|
*
|
|
* I don't differentiate normal deliveries and resends, this
|
|
* implementation will differ from PAPR and not lose such
|
|
* interrupts.
|
|
*/
|
|
if (state->priority == MASKED) {
|
|
state->masked_pending = 1;
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Try the delivery, this will set the need_resend flag
|
|
* in the ICP as part of the atomic transaction if the
|
|
* delivery is not possible.
|
|
*
|
|
* Note that if successful, the new delivery might have itself
|
|
* rejected an interrupt that was "delivered" before we took the
|
|
* ics spin lock.
|
|
*
|
|
* In this case we do the whole sequence all over again for the
|
|
* new guy. We cannot assume that the rejected interrupt is less
|
|
* favored than the new one, and thus doesn't need to be delivered,
|
|
* because by the time we exit icp_rm_try_to_deliver() the target
|
|
* processor may well have already consumed & completed it, and thus
|
|
* the rejected interrupt might actually be already acceptable.
|
|
*/
|
|
if (icp_rm_try_to_deliver(icp, new_irq, state->priority, &reject)) {
|
|
/*
|
|
* Delivery was successful, did we reject somebody else ?
|
|
*/
|
|
if (reject && reject != XICS_IPI) {
|
|
arch_spin_unlock(&ics->lock);
|
|
icp->n_reject++;
|
|
new_irq = reject;
|
|
check_resend = 0;
|
|
goto again;
|
|
}
|
|
} else {
|
|
/*
|
|
* We failed to deliver the interrupt we need to set the
|
|
* resend map bit and mark the ICS state as needing a resend
|
|
*/
|
|
state->resend = 1;
|
|
|
|
/*
|
|
* Make sure when checking resend, we don't miss the resend
|
|
* if resend_map bit is seen and cleared.
|
|
*/
|
|
smp_wmb();
|
|
set_bit(ics->icsid, icp->resend_map);
|
|
|
|
/*
|
|
* If the need_resend flag got cleared in the ICP some time
|
|
* between icp_rm_try_to_deliver() atomic update and now, then
|
|
* we know it might have missed the resend_map bit. So we
|
|
* retry
|
|
*/
|
|
smp_mb();
|
|
if (!icp->state.need_resend) {
|
|
state->resend = 0;
|
|
arch_spin_unlock(&ics->lock);
|
|
check_resend = 0;
|
|
goto again;
|
|
}
|
|
}
|
|
out:
|
|
arch_spin_unlock(&ics->lock);
|
|
}
|
|
|
|
static void icp_rm_down_cppr(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
|
|
u8 new_cppr)
|
|
{
|
|
union kvmppc_icp_state old_state, new_state;
|
|
bool resend;
|
|
|
|
/*
|
|
* This handles several related states in one operation:
|
|
*
|
|
* ICP State: Down_CPPR
|
|
*
|
|
* Load CPPR with new value and if the XISR is 0
|
|
* then check for resends:
|
|
*
|
|
* ICP State: Resend
|
|
*
|
|
* If MFRR is more favored than CPPR, check for IPIs
|
|
* and notify ICS of a potential resend. This is done
|
|
* asynchronously (when used in real mode, we will have
|
|
* to exit here).
|
|
*
|
|
* We do not handle the complete Check_IPI as documented
|
|
* here. In the PAPR, this state will be used for both
|
|
* Set_MFRR and Down_CPPR. However, we know that we aren't
|
|
* changing the MFRR state here so we don't need to handle
|
|
* the case of an MFRR causing a reject of a pending irq,
|
|
* this will have been handled when the MFRR was set in the
|
|
* first place.
|
|
*
|
|
* Thus we don't have to handle rejects, only resends.
|
|
*
|
|
* When implementing real mode for HV KVM, resend will lead to
|
|
* a H_TOO_HARD return and the whole transaction will be handled
|
|
* in virtual mode.
|
|
*/
|
|
do {
|
|
old_state = new_state = READ_ONCE(icp->state);
|
|
|
|
/* Down_CPPR */
|
|
new_state.cppr = new_cppr;
|
|
|
|
/*
|
|
* Cut down Resend / Check_IPI / IPI
|
|
*
|
|
* The logic is that we cannot have a pending interrupt
|
|
* trumped by an IPI at this point (see above), so we
|
|
* know that either the pending interrupt is already an
|
|
* IPI (in which case we don't care to override it) or
|
|
* it's either more favored than us or non existent
|
|
*/
|
|
if (new_state.mfrr < new_cppr &&
|
|
new_state.mfrr <= new_state.pending_pri) {
|
|
new_state.pending_pri = new_state.mfrr;
|
|
new_state.xisr = XICS_IPI;
|
|
}
|
|
|
|
/* Latch/clear resend bit */
|
|
resend = new_state.need_resend;
|
|
new_state.need_resend = 0;
|
|
|
|
} while (!icp_rm_try_update(icp, old_state, new_state));
|
|
|
|
/*
|
|
* Now handle resend checks. Those are asynchronous to the ICP
|
|
* state update in HW (ie bus transactions) so we can handle them
|
|
* separately here as well.
|
|
*/
|
|
if (resend) {
|
|
icp->n_check_resend++;
|
|
icp_rm_check_resend(xics, icp);
|
|
}
|
|
}
|
|
|
|
|
|
unsigned long xics_rm_h_xirr(struct kvm_vcpu *vcpu)
|
|
{
|
|
union kvmppc_icp_state old_state, new_state;
|
|
struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
|
|
struct kvmppc_icp *icp = vcpu->arch.icp;
|
|
u32 xirr;
|
|
|
|
if (!xics || !xics->real_mode)
|
|
return H_TOO_HARD;
|
|
|
|
/* First clear the interrupt */
|
|
icp_rm_clr_vcpu_irq(icp->vcpu);
|
|
|
|
/*
|
|
* ICP State: Accept_Interrupt
|
|
*
|
|
* Return the pending interrupt (if any) along with the
|
|
* current CPPR, then clear the XISR & set CPPR to the
|
|
* pending priority
|
|
*/
|
|
do {
|
|
old_state = new_state = READ_ONCE(icp->state);
|
|
|
|
xirr = old_state.xisr | (((u32)old_state.cppr) << 24);
|
|
if (!old_state.xisr)
|
|
break;
|
|
new_state.cppr = new_state.pending_pri;
|
|
new_state.pending_pri = 0xff;
|
|
new_state.xisr = 0;
|
|
|
|
} while (!icp_rm_try_update(icp, old_state, new_state));
|
|
|
|
/* Return the result in GPR4 */
|
|
vcpu->arch.regs.gpr[4] = xirr;
|
|
|
|
return check_too_hard(xics, icp);
|
|
}
|
|
|
|
int xics_rm_h_ipi(struct kvm_vcpu *vcpu, unsigned long server,
|
|
unsigned long mfrr)
|
|
{
|
|
union kvmppc_icp_state old_state, new_state;
|
|
struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
|
|
struct kvmppc_icp *icp, *this_icp = vcpu->arch.icp;
|
|
u32 reject;
|
|
bool resend;
|
|
bool local;
|
|
|
|
if (!xics || !xics->real_mode)
|
|
return H_TOO_HARD;
|
|
|
|
local = this_icp->server_num == server;
|
|
if (local)
|
|
icp = this_icp;
|
|
else
|
|
icp = kvmppc_xics_find_server(vcpu->kvm, server);
|
|
if (!icp)
|
|
return H_PARAMETER;
|
|
|
|
/*
|
|
* ICP state: Set_MFRR
|
|
*
|
|
* If the CPPR is more favored than the new MFRR, then
|
|
* nothing needs to be done as there can be no XISR to
|
|
* reject.
|
|
*
|
|
* ICP state: Check_IPI
|
|
*
|
|
* If the CPPR is less favored, then we might be replacing
|
|
* an interrupt, and thus need to possibly reject it.
|
|
*
|
|
* ICP State: IPI
|
|
*
|
|
* Besides rejecting any pending interrupts, we also
|
|
* update XISR and pending_pri to mark IPI as pending.
|
|
*
|
|
* PAPR does not describe this state, but if the MFRR is being
|
|
* made less favored than its earlier value, there might be
|
|
* a previously-rejected interrupt needing to be resent.
|
|
* Ideally, we would want to resend only if
|
|
* prio(pending_interrupt) < mfrr &&
|
|
* prio(pending_interrupt) < cppr
|
|
* where pending interrupt is the one that was rejected. But
|
|
* we don't have that state, so we simply trigger a resend
|
|
* whenever the MFRR is made less favored.
|
|
*/
|
|
do {
|
|
old_state = new_state = READ_ONCE(icp->state);
|
|
|
|
/* Set_MFRR */
|
|
new_state.mfrr = mfrr;
|
|
|
|
/* Check_IPI */
|
|
reject = 0;
|
|
resend = false;
|
|
if (mfrr < new_state.cppr) {
|
|
/* Reject a pending interrupt if not an IPI */
|
|
if (mfrr <= new_state.pending_pri) {
|
|
reject = new_state.xisr;
|
|
new_state.pending_pri = mfrr;
|
|
new_state.xisr = XICS_IPI;
|
|
}
|
|
}
|
|
|
|
if (mfrr > old_state.mfrr) {
|
|
resend = new_state.need_resend;
|
|
new_state.need_resend = 0;
|
|
}
|
|
} while (!icp_rm_try_update(icp, old_state, new_state));
|
|
|
|
/* Handle reject in real mode */
|
|
if (reject && reject != XICS_IPI) {
|
|
this_icp->n_reject++;
|
|
icp_rm_deliver_irq(xics, icp, reject, false);
|
|
}
|
|
|
|
/* Handle resends in real mode */
|
|
if (resend) {
|
|
this_icp->n_check_resend++;
|
|
icp_rm_check_resend(xics, icp);
|
|
}
|
|
|
|
return check_too_hard(xics, this_icp);
|
|
}
|
|
|
|
int xics_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr)
|
|
{
|
|
union kvmppc_icp_state old_state, new_state;
|
|
struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
|
|
struct kvmppc_icp *icp = vcpu->arch.icp;
|
|
u32 reject;
|
|
|
|
if (!xics || !xics->real_mode)
|
|
return H_TOO_HARD;
|
|
|
|
/*
|
|
* ICP State: Set_CPPR
|
|
*
|
|
* We can safely compare the new value with the current
|
|
* value outside of the transaction as the CPPR is only
|
|
* ever changed by the processor on itself
|
|
*/
|
|
if (cppr > icp->state.cppr) {
|
|
icp_rm_down_cppr(xics, icp, cppr);
|
|
goto bail;
|
|
} else if (cppr == icp->state.cppr)
|
|
return H_SUCCESS;
|
|
|
|
/*
|
|
* ICP State: Up_CPPR
|
|
*
|
|
* The processor is raising its priority, this can result
|
|
* in a rejection of a pending interrupt:
|
|
*
|
|
* ICP State: Reject_Current
|
|
*
|
|
* We can remove EE from the current processor, the update
|
|
* transaction will set it again if needed
|
|
*/
|
|
icp_rm_clr_vcpu_irq(icp->vcpu);
|
|
|
|
do {
|
|
old_state = new_state = READ_ONCE(icp->state);
|
|
|
|
reject = 0;
|
|
new_state.cppr = cppr;
|
|
|
|
if (cppr <= new_state.pending_pri) {
|
|
reject = new_state.xisr;
|
|
new_state.xisr = 0;
|
|
new_state.pending_pri = 0xff;
|
|
}
|
|
|
|
} while (!icp_rm_try_update(icp, old_state, new_state));
|
|
|
|
/*
|
|
* Check for rejects. They are handled by doing a new delivery
|
|
* attempt (see comments in icp_rm_deliver_irq).
|
|
*/
|
|
if (reject && reject != XICS_IPI) {
|
|
icp->n_reject++;
|
|
icp_rm_deliver_irq(xics, icp, reject, false);
|
|
}
|
|
bail:
|
|
return check_too_hard(xics, icp);
|
|
}
|
|
|
|
static int ics_rm_eoi(struct kvm_vcpu *vcpu, u32 irq)
|
|
{
|
|
struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
|
|
struct kvmppc_icp *icp = vcpu->arch.icp;
|
|
struct kvmppc_ics *ics;
|
|
struct ics_irq_state *state;
|
|
u16 src;
|
|
u32 pq_old, pq_new;
|
|
|
|
/*
|
|
* ICS EOI handling: For LSI, if P bit is still set, we need to
|
|
* resend it.
|
|
*
|
|
* For MSI, we move Q bit into P (and clear Q). If it is set,
|
|
* resend it.
|
|
*/
|
|
|
|
ics = kvmppc_xics_find_ics(xics, irq, &src);
|
|
if (!ics)
|
|
goto bail;
|
|
|
|
state = &ics->irq_state[src];
|
|
|
|
if (state->lsi)
|
|
pq_new = state->pq_state;
|
|
else
|
|
do {
|
|
pq_old = state->pq_state;
|
|
pq_new = pq_old >> 1;
|
|
} while (cmpxchg(&state->pq_state, pq_old, pq_new) != pq_old);
|
|
|
|
if (pq_new & PQ_PRESENTED)
|
|
icp_rm_deliver_irq(xics, NULL, irq, false);
|
|
|
|
if (!hlist_empty(&vcpu->kvm->irq_ack_notifier_list)) {
|
|
icp->rm_action |= XICS_RM_NOTIFY_EOI;
|
|
icp->rm_eoied_irq = irq;
|
|
}
|
|
|
|
if (state->host_irq) {
|
|
++vcpu->stat.pthru_all;
|
|
if (state->intr_cpu != -1) {
|
|
int pcpu = raw_smp_processor_id();
|
|
|
|
pcpu = cpu_first_thread_sibling(pcpu);
|
|
++vcpu->stat.pthru_host;
|
|
if (state->intr_cpu != pcpu) {
|
|
++vcpu->stat.pthru_bad_aff;
|
|
xics_opal_set_server(state->host_irq, pcpu);
|
|
}
|
|
state->intr_cpu = -1;
|
|
}
|
|
}
|
|
|
|
bail:
|
|
return check_too_hard(xics, icp);
|
|
}
|
|
|
|
int xics_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
|
|
{
|
|
struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
|
|
struct kvmppc_icp *icp = vcpu->arch.icp;
|
|
u32 irq = xirr & 0x00ffffff;
|
|
|
|
if (!xics || !xics->real_mode)
|
|
return H_TOO_HARD;
|
|
|
|
/*
|
|
* ICP State: EOI
|
|
*
|
|
* Note: If EOI is incorrectly used by SW to lower the CPPR
|
|
* value (ie more favored), we do not check for rejection of
|
|
* a pending interrupt, this is a SW error and PAPR specifies
|
|
* that we don't have to deal with it.
|
|
*
|
|
* The sending of an EOI to the ICS is handled after the
|
|
* CPPR update
|
|
*
|
|
* ICP State: Down_CPPR which we handle
|
|
* in a separate function as it's shared with H_CPPR.
|
|
*/
|
|
icp_rm_down_cppr(xics, icp, xirr >> 24);
|
|
|
|
/* IPIs have no EOI */
|
|
if (irq == XICS_IPI)
|
|
return check_too_hard(xics, icp);
|
|
|
|
return ics_rm_eoi(vcpu, irq);
|
|
}
|
|
|
|
unsigned long eoi_rc;
|
|
|
|
static void icp_eoi(struct irq_chip *c, u32 hwirq, __be32 xirr, bool *again)
|
|
{
|
|
void __iomem *xics_phys;
|
|
int64_t rc;
|
|
|
|
if (kvmhv_on_pseries()) {
|
|
unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
|
|
|
|
iosync();
|
|
plpar_hcall_raw(H_EOI, retbuf, hwirq);
|
|
return;
|
|
}
|
|
|
|
rc = pnv_opal_pci_msi_eoi(c, hwirq);
|
|
|
|
if (rc)
|
|
eoi_rc = rc;
|
|
|
|
iosync();
|
|
|
|
/* EOI it */
|
|
xics_phys = local_paca->kvm_hstate.xics_phys;
|
|
if (xics_phys) {
|
|
__raw_rm_writel(xirr, xics_phys + XICS_XIRR);
|
|
} else {
|
|
rc = opal_int_eoi(be32_to_cpu(xirr));
|
|
*again = rc > 0;
|
|
}
|
|
}
|
|
|
|
static int xics_opal_set_server(unsigned int hw_irq, int server_cpu)
|
|
{
|
|
unsigned int mangle_cpu = get_hard_smp_processor_id(server_cpu) << 2;
|
|
|
|
return opal_set_xive(hw_irq, mangle_cpu, DEFAULT_PRIORITY);
|
|
}
|
|
|
|
/*
|
|
* Increment a per-CPU 32-bit unsigned integer variable.
|
|
* Safe to call in real-mode. Handles vmalloc'ed addresses
|
|
*
|
|
* ToDo: Make this work for any integral type
|
|
*/
|
|
|
|
static inline void this_cpu_inc_rm(unsigned int __percpu *addr)
|
|
{
|
|
unsigned long l;
|
|
unsigned int *raddr;
|
|
int cpu = smp_processor_id();
|
|
|
|
raddr = per_cpu_ptr(addr, cpu);
|
|
l = (unsigned long)raddr;
|
|
|
|
if (get_region_id(l) == VMALLOC_REGION_ID) {
|
|
l = vmalloc_to_phys(raddr);
|
|
raddr = (unsigned int *)l;
|
|
}
|
|
++*raddr;
|
|
}
|
|
|
|
/*
|
|
* We don't try to update the flags in the irq_desc 'istate' field in
|
|
* here as would happen in the normal IRQ handling path for several reasons:
|
|
* - state flags represent internal IRQ state and are not expected to be
|
|
* updated outside the IRQ subsystem
|
|
* - more importantly, these are useful for edge triggered interrupts,
|
|
* IRQ probing, etc., but we are only handling MSI/MSIx interrupts here
|
|
* and these states shouldn't apply to us.
|
|
*
|
|
* However, we do update irq_stats - we somewhat duplicate the code in
|
|
* kstat_incr_irqs_this_cpu() for this since this function is defined
|
|
* in irq/internal.h which we don't want to include here.
|
|
* The only difference is that desc->kstat_irqs is an allocated per CPU
|
|
* variable and could have been vmalloc'ed, so we can't directly
|
|
* call __this_cpu_inc() on it. The kstat structure is a static
|
|
* per CPU variable and it should be accessible by real-mode KVM.
|
|
*
|
|
*/
|
|
static void kvmppc_rm_handle_irq_desc(struct irq_desc *desc)
|
|
{
|
|
this_cpu_inc_rm(desc->kstat_irqs);
|
|
__this_cpu_inc(kstat.irqs_sum);
|
|
}
|
|
|
|
long kvmppc_deliver_irq_passthru(struct kvm_vcpu *vcpu,
|
|
__be32 xirr,
|
|
struct kvmppc_irq_map *irq_map,
|
|
struct kvmppc_passthru_irqmap *pimap,
|
|
bool *again)
|
|
{
|
|
struct kvmppc_xics *xics;
|
|
struct kvmppc_icp *icp;
|
|
struct kvmppc_ics *ics;
|
|
struct ics_irq_state *state;
|
|
u32 irq;
|
|
u16 src;
|
|
u32 pq_old, pq_new;
|
|
|
|
irq = irq_map->v_hwirq;
|
|
xics = vcpu->kvm->arch.xics;
|
|
icp = vcpu->arch.icp;
|
|
|
|
kvmppc_rm_handle_irq_desc(irq_map->desc);
|
|
|
|
ics = kvmppc_xics_find_ics(xics, irq, &src);
|
|
if (!ics)
|
|
return 2;
|
|
|
|
state = &ics->irq_state[src];
|
|
|
|
/* only MSIs register bypass producers, so it must be MSI here */
|
|
do {
|
|
pq_old = state->pq_state;
|
|
pq_new = ((pq_old << 1) & 3) | PQ_PRESENTED;
|
|
} while (cmpxchg(&state->pq_state, pq_old, pq_new) != pq_old);
|
|
|
|
/* Test P=1, Q=0, this is the only case where we present */
|
|
if (pq_new == PQ_PRESENTED)
|
|
icp_rm_deliver_irq(xics, icp, irq, false);
|
|
|
|
/* EOI the interrupt */
|
|
icp_eoi(irq_desc_get_chip(irq_map->desc), irq_map->r_hwirq, xirr,
|
|
again);
|
|
|
|
if (check_too_hard(xics, icp) == H_TOO_HARD)
|
|
return 2;
|
|
else
|
|
return -2;
|
|
}
|
|
|
|
/* --- Non-real mode XICS-related built-in routines --- */
|
|
|
|
/**
|
|
* Host Operations poked by RM KVM
|
|
*/
|
|
static void rm_host_ipi_action(int action, void *data)
|
|
{
|
|
switch (action) {
|
|
case XICS_RM_KICK_VCPU:
|
|
kvmppc_host_rm_ops_hv->vcpu_kick(data);
|
|
break;
|
|
default:
|
|
WARN(1, "Unexpected rm_action=%d data=%p\n", action, data);
|
|
break;
|
|
}
|
|
|
|
}
|
|
|
|
void kvmppc_xics_ipi_action(void)
|
|
{
|
|
int core;
|
|
unsigned int cpu = smp_processor_id();
|
|
struct kvmppc_host_rm_core *rm_corep;
|
|
|
|
core = cpu >> threads_shift;
|
|
rm_corep = &kvmppc_host_rm_ops_hv->rm_core[core];
|
|
|
|
if (rm_corep->rm_data) {
|
|
rm_host_ipi_action(rm_corep->rm_state.rm_action,
|
|
rm_corep->rm_data);
|
|
/* Order these stores against the real mode KVM */
|
|
rm_corep->rm_data = NULL;
|
|
smp_wmb();
|
|
rm_corep->rm_state.rm_action = 0;
|
|
}
|
|
}
|