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![Claudiu Beznea](/assets/img/avatar_default.png)
Commitfacb87ad75
("clk: at91: sama7g5: remove prescaler part of master clock") removed the master clock's prescaler from clock tree of SAMA7G5 as it has been discovered that there is a hardware bug when trying to change it at run-time (bug is described in description of commitfacb87ad75
("clk: at91: sama7g5: remove prescaler part of master clock")). This was previously changed at CPUFreq driver request. Thus, with commitfacb87ad75
("clk: at91: sama7g5: remove prescaler part of master clock") there is no need of code that handles run-time changes of master clock's prescaler, thus remove this code. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220203110202.18329-1-claudiu.beznea@microchip.com
189 lines
4.7 KiB
C
189 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/clk-provider.h>
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#include <linux/mfd/syscon.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/at91.h>
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#include "pmc.h"
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static DEFINE_SPINLOCK(sam9rl_mck_lock);
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static const struct clk_master_characteristics sam9rl_mck_characteristics = {
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.output = { .min = 0, .max = 94000000 },
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.divisors = { 1, 2, 4, 0 },
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};
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static u8 sam9rl_plla_out[] = { 0, 2 };
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static const struct clk_range sam9rl_plla_outputs[] = {
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{ .min = 80000000, .max = 200000000 },
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{ .min = 190000000, .max = 240000000 },
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};
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static const struct clk_pll_characteristics sam9rl_plla_characteristics = {
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.input = { .min = 1000000, .max = 32000000 },
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.num_output = ARRAY_SIZE(sam9rl_plla_outputs),
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.output = sam9rl_plla_outputs,
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.out = sam9rl_plla_out,
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};
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static const struct {
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char *n;
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char *p;
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u8 id;
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} at91sam9rl_systemck[] = {
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{ .n = "pck0", .p = "prog0", .id = 8 },
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{ .n = "pck1", .p = "prog1", .id = 9 },
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};
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static const struct {
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char *n;
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u8 id;
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} at91sam9rl_periphck[] = {
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{ .n = "pioA_clk", .id = 2, },
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{ .n = "pioB_clk", .id = 3, },
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{ .n = "pioC_clk", .id = 4, },
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{ .n = "pioD_clk", .id = 5, },
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{ .n = "usart0_clk", .id = 6, },
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{ .n = "usart1_clk", .id = 7, },
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{ .n = "usart2_clk", .id = 8, },
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{ .n = "usart3_clk", .id = 9, },
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{ .n = "mci0_clk", .id = 10, },
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{ .n = "twi0_clk", .id = 11, },
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{ .n = "twi1_clk", .id = 12, },
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{ .n = "spi0_clk", .id = 13, },
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{ .n = "ssc0_clk", .id = 14, },
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{ .n = "ssc1_clk", .id = 15, },
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{ .n = "tc0_clk", .id = 16, },
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{ .n = "tc1_clk", .id = 17, },
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{ .n = "tc2_clk", .id = 18, },
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{ .n = "pwm_clk", .id = 19, },
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{ .n = "adc_clk", .id = 20, },
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{ .n = "dma0_clk", .id = 21, },
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{ .n = "udphs_clk", .id = 22, },
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{ .n = "lcd_clk", .id = 23, },
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};
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static void __init at91sam9rl_pmc_setup(struct device_node *np)
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{
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const char *slck_name, *mainxtal_name;
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struct pmc_data *at91sam9rl_pmc;
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const char *parent_names[6];
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struct regmap *regmap;
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struct clk_hw *hw;
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int i;
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i = of_property_match_string(np, "clock-names", "slow_clk");
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if (i < 0)
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return;
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slck_name = of_clk_get_parent_name(np, i);
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i = of_property_match_string(np, "clock-names", "main_xtal");
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if (i < 0)
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return;
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mainxtal_name = of_clk_get_parent_name(np, i);
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regmap = device_node_to_regmap(np);
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if (IS_ERR(regmap))
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return;
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at91sam9rl_pmc = pmc_data_allocate(PMC_PLLACK + 1,
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nck(at91sam9rl_systemck),
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nck(at91sam9rl_periphck), 0, 2);
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if (!at91sam9rl_pmc)
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return;
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hw = at91_clk_register_rm9200_main(regmap, "mainck", mainxtal_name);
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if (IS_ERR(hw))
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goto err_free;
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at91sam9rl_pmc->chws[PMC_MAIN] = hw;
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hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
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&at91rm9200_pll_layout,
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&sam9rl_plla_characteristics);
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if (IS_ERR(hw))
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goto err_free;
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at91sam9rl_pmc->chws[PMC_PLLACK] = hw;
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hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
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if (IS_ERR(hw))
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goto err_free;
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at91sam9rl_pmc->chws[PMC_UTMI] = hw;
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parent_names[0] = slck_name;
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parent_names[1] = "mainck";
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parent_names[2] = "pllack";
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parent_names[3] = "utmick";
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hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
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parent_names,
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&at91rm9200_master_layout,
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&sam9rl_mck_characteristics,
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&sam9rl_mck_lock);
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if (IS_ERR(hw))
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goto err_free;
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hw = at91_clk_register_master_div(regmap, "masterck_div",
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"masterck_pres",
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&at91rm9200_master_layout,
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&sam9rl_mck_characteristics,
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&sam9rl_mck_lock, CLK_SET_RATE_GATE, 0);
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if (IS_ERR(hw))
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goto err_free;
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at91sam9rl_pmc->chws[PMC_MCK] = hw;
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parent_names[0] = slck_name;
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parent_names[1] = "mainck";
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parent_names[2] = "pllack";
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parent_names[3] = "utmick";
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parent_names[4] = "masterck_div";
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for (i = 0; i < 2; i++) {
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char name[6];
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snprintf(name, sizeof(name), "prog%d", i);
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hw = at91_clk_register_programmable(regmap, name,
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parent_names, 5, i,
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&at91rm9200_programmable_layout,
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NULL);
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if (IS_ERR(hw))
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goto err_free;
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at91sam9rl_pmc->pchws[i] = hw;
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}
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for (i = 0; i < ARRAY_SIZE(at91sam9rl_systemck); i++) {
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hw = at91_clk_register_system(regmap, at91sam9rl_systemck[i].n,
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at91sam9rl_systemck[i].p,
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at91sam9rl_systemck[i].id);
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if (IS_ERR(hw))
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goto err_free;
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at91sam9rl_pmc->shws[at91sam9rl_systemck[i].id] = hw;
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}
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for (i = 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) {
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hw = at91_clk_register_peripheral(regmap,
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at91sam9rl_periphck[i].n,
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"masterck_div",
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at91sam9rl_periphck[i].id);
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if (IS_ERR(hw))
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goto err_free;
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at91sam9rl_pmc->phws[at91sam9rl_periphck[i].id] = hw;
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}
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of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9rl_pmc);
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return;
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err_free:
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kfree(at91sam9rl_pmc);
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}
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CLK_OF_DECLARE(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup);
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