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![Claudiu Beznea](/assets/img/avatar_default.png)
SAMA5D2 and SAMA7G5 have a special power saving mode (backup mode) where most of the SoC's components are powered off (including PMC). Resuming from this mode is done with the help of bootloader. Peripherals are not aware of the power saving mode thus most of them are disabling clocks in proper suspend API and re-enable them in resume API without taking into account the previously setup rate. Moreover some of the peripherals are acting as wakeup sources and are not disabling the clocks in this scenario, when suspending. Since backup mode cuts the power for peripherals, in resume part these clocks needs to be re-configured. The initial PMC suspend/resume code was designed only for SAMA5D2's PMC (as it was the only one supporting backup mode). SAMA7G supports also backup mode and its PMC is different (few new functionalities, different registers offsets, different offsets in registers for each functionalities). To address both SAMA5D2 and SAMA7G5 PMC add .save_context()/.resume_context() support to each clocks driver and call this from PMC driver. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-2-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
286 lines
6.1 KiB
C
286 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/of.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <soc/at91/atmel-sfr.h>
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#include "pmc.h"
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/*
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* The purpose of this clock is to generate a 480 MHz signal. A different
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* rate can't be configured.
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*/
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#define UTMI_RATE 480000000
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struct clk_utmi {
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struct clk_hw hw;
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struct regmap *regmap_pmc;
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struct regmap *regmap_sfr;
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struct at91_clk_pms pms;
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};
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#define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw)
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static inline bool clk_utmi_ready(struct regmap *regmap)
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{
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unsigned int status;
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regmap_read(regmap, AT91_PMC_SR, &status);
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return status & AT91_PMC_LOCKU;
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}
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static int clk_utmi_prepare(struct clk_hw *hw)
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{
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struct clk_hw *hw_parent;
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struct clk_utmi *utmi = to_clk_utmi(hw);
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unsigned int uckr = AT91_PMC_UPLLEN | AT91_PMC_UPLLCOUNT |
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AT91_PMC_BIASEN;
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unsigned int utmi_ref_clk_freq;
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unsigned long parent_rate;
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/*
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* If mainck rate is different from 12 MHz, we have to configure the
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* FREQ field of the SFR_UTMICKTRIM register to generate properly
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* the utmi clock.
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*/
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hw_parent = clk_hw_get_parent(hw);
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parent_rate = clk_hw_get_rate(hw_parent);
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switch (parent_rate) {
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case 12000000:
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utmi_ref_clk_freq = 0;
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break;
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case 16000000:
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utmi_ref_clk_freq = 1;
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break;
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case 24000000:
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utmi_ref_clk_freq = 2;
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break;
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/*
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* Not supported on SAMA5D2 but it's not an issue since MAINCK
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* maximum value is 24 MHz.
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*/
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case 48000000:
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utmi_ref_clk_freq = 3;
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break;
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default:
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pr_err("UTMICK: unsupported mainck rate\n");
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return -EINVAL;
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}
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if (utmi->regmap_sfr) {
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regmap_update_bits(utmi->regmap_sfr, AT91_SFR_UTMICKTRIM,
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AT91_UTMICKTRIM_FREQ, utmi_ref_clk_freq);
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} else if (utmi_ref_clk_freq) {
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pr_err("UTMICK: sfr node required\n");
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return -EINVAL;
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}
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regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, uckr, uckr);
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while (!clk_utmi_ready(utmi->regmap_pmc))
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cpu_relax();
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return 0;
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}
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static int clk_utmi_is_prepared(struct clk_hw *hw)
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{
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struct clk_utmi *utmi = to_clk_utmi(hw);
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return clk_utmi_ready(utmi->regmap_pmc);
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}
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static void clk_utmi_unprepare(struct clk_hw *hw)
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{
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struct clk_utmi *utmi = to_clk_utmi(hw);
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regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR,
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AT91_PMC_UPLLEN, 0);
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}
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static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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/* UTMI clk rate is fixed. */
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return UTMI_RATE;
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}
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static int clk_utmi_save_context(struct clk_hw *hw)
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{
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struct clk_utmi *utmi = to_clk_utmi(hw);
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utmi->pms.status = clk_utmi_is_prepared(hw);
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return 0;
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}
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static void clk_utmi_restore_context(struct clk_hw *hw)
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{
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struct clk_utmi *utmi = to_clk_utmi(hw);
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if (utmi->pms.status)
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clk_utmi_prepare(hw);
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}
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static const struct clk_ops utmi_ops = {
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.prepare = clk_utmi_prepare,
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.unprepare = clk_utmi_unprepare,
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.is_prepared = clk_utmi_is_prepared,
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.recalc_rate = clk_utmi_recalc_rate,
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.save_context = clk_utmi_save_context,
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.restore_context = clk_utmi_restore_context,
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};
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static struct clk_hw * __init
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at91_clk_register_utmi_internal(struct regmap *regmap_pmc,
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struct regmap *regmap_sfr,
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const char *name, const char *parent_name,
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const struct clk_ops *ops, unsigned long flags)
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{
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struct clk_utmi *utmi;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
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if (!utmi)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = ops;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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init.flags = flags;
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utmi->hw.init = &init;
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utmi->regmap_pmc = regmap_pmc;
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utmi->regmap_sfr = regmap_sfr;
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hw = &utmi->hw;
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ret = clk_hw_register(NULL, &utmi->hw);
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if (ret) {
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kfree(utmi);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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struct clk_hw * __init
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at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
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const char *name, const char *parent_name)
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{
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return at91_clk_register_utmi_internal(regmap_pmc, regmap_sfr, name,
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parent_name, &utmi_ops, CLK_SET_RATE_GATE);
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}
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static int clk_utmi_sama7g5_prepare(struct clk_hw *hw)
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{
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struct clk_utmi *utmi = to_clk_utmi(hw);
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struct clk_hw *hw_parent;
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unsigned long parent_rate;
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unsigned int val;
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hw_parent = clk_hw_get_parent(hw);
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parent_rate = clk_hw_get_rate(hw_parent);
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switch (parent_rate) {
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case 16000000:
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val = 0;
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break;
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case 20000000:
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val = 2;
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break;
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case 24000000:
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val = 3;
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break;
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case 32000000:
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val = 5;
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break;
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default:
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pr_err("UTMICK: unsupported main_xtal rate\n");
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return -EINVAL;
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}
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regmap_write(utmi->regmap_pmc, AT91_PMC_XTALF, val);
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return 0;
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}
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static int clk_utmi_sama7g5_is_prepared(struct clk_hw *hw)
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{
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struct clk_utmi *utmi = to_clk_utmi(hw);
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struct clk_hw *hw_parent;
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unsigned long parent_rate;
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unsigned int val;
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hw_parent = clk_hw_get_parent(hw);
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parent_rate = clk_hw_get_rate(hw_parent);
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regmap_read(utmi->regmap_pmc, AT91_PMC_XTALF, &val);
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switch (val & 0x7) {
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case 0:
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if (parent_rate == 16000000)
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return 1;
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break;
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case 2:
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if (parent_rate == 20000000)
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return 1;
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break;
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case 3:
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if (parent_rate == 24000000)
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return 1;
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break;
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case 5:
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if (parent_rate == 32000000)
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return 1;
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break;
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default:
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break;
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}
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return 0;
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}
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static int clk_utmi_sama7g5_save_context(struct clk_hw *hw)
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{
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struct clk_utmi *utmi = to_clk_utmi(hw);
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utmi->pms.status = clk_utmi_sama7g5_is_prepared(hw);
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return 0;
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}
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static void clk_utmi_sama7g5_restore_context(struct clk_hw *hw)
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{
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struct clk_utmi *utmi = to_clk_utmi(hw);
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if (utmi->pms.status)
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clk_utmi_sama7g5_prepare(hw);
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}
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static const struct clk_ops sama7g5_utmi_ops = {
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.prepare = clk_utmi_sama7g5_prepare,
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.is_prepared = clk_utmi_sama7g5_is_prepared,
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.recalc_rate = clk_utmi_recalc_rate,
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.save_context = clk_utmi_sama7g5_save_context,
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.restore_context = clk_utmi_sama7g5_restore_context,
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};
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struct clk_hw * __init
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at91_clk_sama7g5_register_utmi(struct regmap *regmap_pmc, const char *name,
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const char *parent_name)
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{
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return at91_clk_register_utmi_internal(regmap_pmc, NULL, name,
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parent_name, &sama7g5_utmi_ops, 0);
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}
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