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![Colin Ian King](/assets/img/avatar_default.png)
The variable divider is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20200602172435.70282-1-colin.king@canonical.com Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
602 lines
15 KiB
C
602 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
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*
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* Authors:
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* Serge Semin <Sergey.Semin@baikalelectronics.ru>
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* Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
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*
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* Baikal-T1 CCU Dividers interface driver
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*/
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#define pr_fmt(fmt) "bt1-ccu-div: " fmt
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#include <linux/kernel.h>
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#include <linux/printk.h>
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#include <linux/bits.h>
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#include <linux/bitfield.h>
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#include <linux/slab.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/spinlock.h>
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#include <linux/regmap.h>
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#include <linux/delay.h>
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#include <linux/time64.h>
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#include <linux/debugfs.h>
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#include "ccu-div.h"
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#define CCU_DIV_CTL 0x00
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#define CCU_DIV_CTL_EN BIT(0)
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#define CCU_DIV_CTL_RST BIT(1)
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#define CCU_DIV_CTL_SET_CLKDIV BIT(2)
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#define CCU_DIV_CTL_CLKDIV_FLD 4
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#define CCU_DIV_CTL_CLKDIV_MASK(_width) \
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GENMASK((_width) + CCU_DIV_CTL_CLKDIV_FLD - 1, CCU_DIV_CTL_CLKDIV_FLD)
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#define CCU_DIV_CTL_LOCK_SHIFTED BIT(27)
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#define CCU_DIV_CTL_LOCK_NORMAL BIT(31)
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#define CCU_DIV_RST_DELAY_US 1
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#define CCU_DIV_LOCK_CHECK_RETRIES 50
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#define CCU_DIV_CLKDIV_MIN 0
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#define CCU_DIV_CLKDIV_MAX(_mask) \
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((_mask) >> CCU_DIV_CTL_CLKDIV_FLD)
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/*
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* Use the next two methods until there are generic field setter and
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* getter available with non-constant mask support.
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*/
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static inline u32 ccu_div_get(u32 mask, u32 val)
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{
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return (val & mask) >> CCU_DIV_CTL_CLKDIV_FLD;
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}
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static inline u32 ccu_div_prep(u32 mask, u32 val)
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{
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return (val << CCU_DIV_CTL_CLKDIV_FLD) & mask;
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}
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static inline unsigned long ccu_div_lock_delay_ns(unsigned long ref_clk,
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unsigned long div)
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{
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u64 ns = 4ULL * (div ?: 1) * NSEC_PER_SEC;
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do_div(ns, ref_clk);
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return ns;
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}
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static inline unsigned long ccu_div_calc_freq(unsigned long ref_clk,
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unsigned long div)
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{
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return ref_clk / (div ?: 1);
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}
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static int ccu_div_var_update_clkdiv(struct ccu_div *div,
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unsigned long parent_rate,
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unsigned long divider)
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{
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unsigned long nd;
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u32 val = 0;
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u32 lock;
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int count;
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nd = ccu_div_lock_delay_ns(parent_rate, divider);
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if (div->features & CCU_DIV_LOCK_SHIFTED)
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lock = CCU_DIV_CTL_LOCK_SHIFTED;
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else
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lock = CCU_DIV_CTL_LOCK_NORMAL;
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regmap_update_bits(div->sys_regs, div->reg_ctl,
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CCU_DIV_CTL_SET_CLKDIV, CCU_DIV_CTL_SET_CLKDIV);
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/*
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* Until there is nsec-version of readl_poll_timeout() is available
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* we have to implement the next polling loop.
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*/
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count = CCU_DIV_LOCK_CHECK_RETRIES;
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do {
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ndelay(nd);
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regmap_read(div->sys_regs, div->reg_ctl, &val);
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if (val & lock)
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return 0;
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} while (--count);
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return -ETIMEDOUT;
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}
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static int ccu_div_var_enable(struct clk_hw *hw)
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{
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struct clk_hw *parent_hw = clk_hw_get_parent(hw);
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struct ccu_div *div = to_ccu_div(hw);
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unsigned long flags;
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u32 val = 0;
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int ret;
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if (!parent_hw) {
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pr_err("Can't enable '%s' with no parent", clk_hw_get_name(hw));
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return -EINVAL;
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}
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regmap_read(div->sys_regs, div->reg_ctl, &val);
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if (val & CCU_DIV_CTL_EN)
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return 0;
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spin_lock_irqsave(&div->lock, flags);
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ret = ccu_div_var_update_clkdiv(div, clk_hw_get_rate(parent_hw),
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ccu_div_get(div->mask, val));
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if (!ret)
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regmap_update_bits(div->sys_regs, div->reg_ctl,
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CCU_DIV_CTL_EN, CCU_DIV_CTL_EN);
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spin_unlock_irqrestore(&div->lock, flags);
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if (ret)
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pr_err("Divider '%s' lock timed out\n", clk_hw_get_name(hw));
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return ret;
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}
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static int ccu_div_gate_enable(struct clk_hw *hw)
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{
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struct ccu_div *div = to_ccu_div(hw);
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unsigned long flags;
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spin_lock_irqsave(&div->lock, flags);
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regmap_update_bits(div->sys_regs, div->reg_ctl,
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CCU_DIV_CTL_EN, CCU_DIV_CTL_EN);
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spin_unlock_irqrestore(&div->lock, flags);
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return 0;
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}
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static void ccu_div_gate_disable(struct clk_hw *hw)
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{
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struct ccu_div *div = to_ccu_div(hw);
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unsigned long flags;
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spin_lock_irqsave(&div->lock, flags);
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regmap_update_bits(div->sys_regs, div->reg_ctl, CCU_DIV_CTL_EN, 0);
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spin_unlock_irqrestore(&div->lock, flags);
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}
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static int ccu_div_gate_is_enabled(struct clk_hw *hw)
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{
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struct ccu_div *div = to_ccu_div(hw);
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u32 val = 0;
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regmap_read(div->sys_regs, div->reg_ctl, &val);
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return !!(val & CCU_DIV_CTL_EN);
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}
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static unsigned long ccu_div_var_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ccu_div *div = to_ccu_div(hw);
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unsigned long divider;
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u32 val = 0;
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regmap_read(div->sys_regs, div->reg_ctl, &val);
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divider = ccu_div_get(div->mask, val);
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return ccu_div_calc_freq(parent_rate, divider);
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}
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static inline unsigned long ccu_div_var_calc_divider(unsigned long rate,
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unsigned long parent_rate,
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unsigned int mask)
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{
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unsigned long divider;
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divider = parent_rate / rate;
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return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN,
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CCU_DIV_CLKDIV_MAX(mask));
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}
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static long ccu_div_var_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct ccu_div *div = to_ccu_div(hw);
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unsigned long divider;
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divider = ccu_div_var_calc_divider(rate, *parent_rate, div->mask);
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return ccu_div_calc_freq(*parent_rate, divider);
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}
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/*
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* This method is used for the clock divider blocks, which support the
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* on-the-fly rate change. So due to lacking the EN bit functionality
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* they can't be gated before the rate adjustment.
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*/
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static int ccu_div_var_set_rate_slow(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct ccu_div *div = to_ccu_div(hw);
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unsigned long flags, divider;
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u32 val;
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int ret;
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divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask);
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if (divider == 1 && div->features & CCU_DIV_SKIP_ONE) {
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divider = 0;
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} else if (div->features & CCU_DIV_SKIP_ONE_TO_THREE) {
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if (divider == 1 || divider == 2)
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divider = 0;
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else if (divider == 3)
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divider = 4;
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}
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val = ccu_div_prep(div->mask, divider);
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spin_lock_irqsave(&div->lock, flags);
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regmap_update_bits(div->sys_regs, div->reg_ctl, div->mask, val);
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ret = ccu_div_var_update_clkdiv(div, parent_rate, divider);
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spin_unlock_irqrestore(&div->lock, flags);
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if (ret)
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pr_err("Divider '%s' lock timed out\n", clk_hw_get_name(hw));
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return ret;
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}
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/*
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* This method is used for the clock divider blocks, which don't support
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* the on-the-fly rate change.
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*/
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static int ccu_div_var_set_rate_fast(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct ccu_div *div = to_ccu_div(hw);
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unsigned long flags, divider;
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u32 val;
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divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask);
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val = ccu_div_prep(div->mask, divider);
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/*
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* Also disable the clock divider block if it was enabled by default
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* or by the bootloader.
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*/
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spin_lock_irqsave(&div->lock, flags);
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regmap_update_bits(div->sys_regs, div->reg_ctl,
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div->mask | CCU_DIV_CTL_EN, val);
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spin_unlock_irqrestore(&div->lock, flags);
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return 0;
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}
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static unsigned long ccu_div_fixed_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ccu_div *div = to_ccu_div(hw);
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return ccu_div_calc_freq(parent_rate, div->divider);
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}
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static long ccu_div_fixed_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct ccu_div *div = to_ccu_div(hw);
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return ccu_div_calc_freq(*parent_rate, div->divider);
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}
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static int ccu_div_fixed_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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return 0;
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}
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int ccu_div_reset_domain(struct ccu_div *div)
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{
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unsigned long flags;
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if (!div || !(div->features & CCU_DIV_RESET_DOMAIN))
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return -EINVAL;
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spin_lock_irqsave(&div->lock, flags);
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regmap_update_bits(div->sys_regs, div->reg_ctl,
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CCU_DIV_CTL_RST, CCU_DIV_CTL_RST);
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spin_unlock_irqrestore(&div->lock, flags);
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/* The next delay must be enough to cover all the resets. */
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udelay(CCU_DIV_RST_DELAY_US);
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return 0;
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}
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#ifdef CONFIG_DEBUG_FS
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struct ccu_div_dbgfs_bit {
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struct ccu_div *div;
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const char *name;
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u32 mask;
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};
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#define CCU_DIV_DBGFS_BIT_ATTR(_name, _mask) { \
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.name = _name, \
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.mask = _mask \
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}
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static const struct ccu_div_dbgfs_bit ccu_div_bits[] = {
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CCU_DIV_DBGFS_BIT_ATTR("div_en", CCU_DIV_CTL_EN),
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CCU_DIV_DBGFS_BIT_ATTR("div_rst", CCU_DIV_CTL_RST),
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CCU_DIV_DBGFS_BIT_ATTR("div_bypass", CCU_DIV_CTL_SET_CLKDIV),
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CCU_DIV_DBGFS_BIT_ATTR("div_lock", CCU_DIV_CTL_LOCK_NORMAL)
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};
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#define CCU_DIV_DBGFS_BIT_NUM ARRAY_SIZE(ccu_div_bits)
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/*
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* It can be dangerous to change the Divider settings behind clock framework
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* back, therefore we don't provide any kernel config based compile time option
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* for this feature to enable.
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*/
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#undef CCU_DIV_ALLOW_WRITE_DEBUGFS
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#ifdef CCU_DIV_ALLOW_WRITE_DEBUGFS
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static int ccu_div_dbgfs_bit_set(void *priv, u64 val)
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{
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const struct ccu_div_dbgfs_bit *bit = priv;
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struct ccu_div *div = bit->div;
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unsigned long flags;
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spin_lock_irqsave(&div->lock, flags);
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regmap_update_bits(div->sys_regs, div->reg_ctl,
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bit->mask, val ? bit->mask : 0);
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spin_unlock_irqrestore(&div->lock, flags);
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return 0;
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}
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static int ccu_div_dbgfs_var_clkdiv_set(void *priv, u64 val)
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{
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struct ccu_div *div = priv;
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unsigned long flags;
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u32 data;
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val = clamp_t(u64, val, CCU_DIV_CLKDIV_MIN,
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CCU_DIV_CLKDIV_MAX(div->mask));
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data = ccu_div_prep(div->mask, val);
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spin_lock_irqsave(&div->lock, flags);
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regmap_update_bits(div->sys_regs, div->reg_ctl, div->mask, data);
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spin_unlock_irqrestore(&div->lock, flags);
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return 0;
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}
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#define ccu_div_dbgfs_mode 0644
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#else /* !CCU_DIV_ALLOW_WRITE_DEBUGFS */
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#define ccu_div_dbgfs_bit_set NULL
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#define ccu_div_dbgfs_var_clkdiv_set NULL
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#define ccu_div_dbgfs_mode 0444
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#endif /* !CCU_DIV_ALLOW_WRITE_DEBUGFS */
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static int ccu_div_dbgfs_bit_get(void *priv, u64 *val)
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{
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const struct ccu_div_dbgfs_bit *bit = priv;
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struct ccu_div *div = bit->div;
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u32 data = 0;
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regmap_read(div->sys_regs, div->reg_ctl, &data);
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*val = !!(data & bit->mask);
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return 0;
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}
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DEFINE_DEBUGFS_ATTRIBUTE(ccu_div_dbgfs_bit_fops,
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ccu_div_dbgfs_bit_get, ccu_div_dbgfs_bit_set, "%llu\n");
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static int ccu_div_dbgfs_var_clkdiv_get(void *priv, u64 *val)
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{
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struct ccu_div *div = priv;
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u32 data = 0;
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regmap_read(div->sys_regs, div->reg_ctl, &data);
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*val = ccu_div_get(div->mask, data);
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return 0;
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}
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DEFINE_DEBUGFS_ATTRIBUTE(ccu_div_dbgfs_var_clkdiv_fops,
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ccu_div_dbgfs_var_clkdiv_get, ccu_div_dbgfs_var_clkdiv_set, "%llu\n");
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static int ccu_div_dbgfs_fixed_clkdiv_get(void *priv, u64 *val)
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{
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struct ccu_div *div = priv;
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*val = div->divider;
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return 0;
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}
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DEFINE_DEBUGFS_ATTRIBUTE(ccu_div_dbgfs_fixed_clkdiv_fops,
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ccu_div_dbgfs_fixed_clkdiv_get, NULL, "%llu\n");
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static void ccu_div_var_debug_init(struct clk_hw *hw, struct dentry *dentry)
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{
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struct ccu_div *div = to_ccu_div(hw);
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struct ccu_div_dbgfs_bit *bits;
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int didx, bidx, num = 2;
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const char *name;
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num += !!(div->flags & CLK_SET_RATE_GATE) +
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!!(div->features & CCU_DIV_RESET_DOMAIN);
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bits = kcalloc(num, sizeof(*bits), GFP_KERNEL);
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if (!bits)
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return;
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for (didx = 0, bidx = 0; bidx < CCU_DIV_DBGFS_BIT_NUM; ++bidx) {
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name = ccu_div_bits[bidx].name;
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if (!(div->flags & CLK_SET_RATE_GATE) &&
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!strcmp("div_en", name)) {
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continue;
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}
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if (!(div->features & CCU_DIV_RESET_DOMAIN) &&
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!strcmp("div_rst", name)) {
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continue;
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}
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bits[didx] = ccu_div_bits[bidx];
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bits[didx].div = div;
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if (div->features & CCU_DIV_LOCK_SHIFTED &&
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!strcmp("div_lock", name)) {
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bits[didx].mask = CCU_DIV_CTL_LOCK_SHIFTED;
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}
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debugfs_create_file_unsafe(bits[didx].name, ccu_div_dbgfs_mode,
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dentry, &bits[didx],
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&ccu_div_dbgfs_bit_fops);
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++didx;
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}
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debugfs_create_file_unsafe("div_clkdiv", ccu_div_dbgfs_mode, dentry,
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div, &ccu_div_dbgfs_var_clkdiv_fops);
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}
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static void ccu_div_gate_debug_init(struct clk_hw *hw, struct dentry *dentry)
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{
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struct ccu_div *div = to_ccu_div(hw);
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struct ccu_div_dbgfs_bit *bit;
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bit = kmalloc(sizeof(*bit), GFP_KERNEL);
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if (!bit)
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return;
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*bit = ccu_div_bits[0];
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bit->div = div;
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debugfs_create_file_unsafe(bit->name, ccu_div_dbgfs_mode, dentry, bit,
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&ccu_div_dbgfs_bit_fops);
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debugfs_create_file_unsafe("div_clkdiv", 0400, dentry, div,
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&ccu_div_dbgfs_fixed_clkdiv_fops);
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}
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static void ccu_div_fixed_debug_init(struct clk_hw *hw, struct dentry *dentry)
|
|
{
|
|
struct ccu_div *div = to_ccu_div(hw);
|
|
|
|
debugfs_create_file_unsafe("div_clkdiv", 0400, dentry, div,
|
|
&ccu_div_dbgfs_fixed_clkdiv_fops);
|
|
}
|
|
|
|
#else /* !CONFIG_DEBUG_FS */
|
|
|
|
#define ccu_div_var_debug_init NULL
|
|
#define ccu_div_gate_debug_init NULL
|
|
#define ccu_div_fixed_debug_init NULL
|
|
|
|
#endif /* !CONFIG_DEBUG_FS */
|
|
|
|
static const struct clk_ops ccu_div_var_gate_to_set_ops = {
|
|
.enable = ccu_div_var_enable,
|
|
.disable = ccu_div_gate_disable,
|
|
.is_enabled = ccu_div_gate_is_enabled,
|
|
.recalc_rate = ccu_div_var_recalc_rate,
|
|
.round_rate = ccu_div_var_round_rate,
|
|
.set_rate = ccu_div_var_set_rate_fast,
|
|
.debug_init = ccu_div_var_debug_init
|
|
};
|
|
|
|
static const struct clk_ops ccu_div_var_nogate_ops = {
|
|
.recalc_rate = ccu_div_var_recalc_rate,
|
|
.round_rate = ccu_div_var_round_rate,
|
|
.set_rate = ccu_div_var_set_rate_slow,
|
|
.debug_init = ccu_div_var_debug_init
|
|
};
|
|
|
|
static const struct clk_ops ccu_div_gate_ops = {
|
|
.enable = ccu_div_gate_enable,
|
|
.disable = ccu_div_gate_disable,
|
|
.is_enabled = ccu_div_gate_is_enabled,
|
|
.recalc_rate = ccu_div_fixed_recalc_rate,
|
|
.round_rate = ccu_div_fixed_round_rate,
|
|
.set_rate = ccu_div_fixed_set_rate,
|
|
.debug_init = ccu_div_gate_debug_init
|
|
};
|
|
|
|
static const struct clk_ops ccu_div_fixed_ops = {
|
|
.recalc_rate = ccu_div_fixed_recalc_rate,
|
|
.round_rate = ccu_div_fixed_round_rate,
|
|
.set_rate = ccu_div_fixed_set_rate,
|
|
.debug_init = ccu_div_fixed_debug_init
|
|
};
|
|
|
|
struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *div_init)
|
|
{
|
|
struct clk_parent_data parent_data = { };
|
|
struct clk_init_data hw_init = { };
|
|
struct ccu_div *div;
|
|
int ret;
|
|
|
|
if (!div_init)
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
div = kzalloc(sizeof(*div), GFP_KERNEL);
|
|
if (!div)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
/*
|
|
* Note since Baikal-T1 System Controller registers are MMIO-backed
|
|
* we won't check the regmap IO operations return status, because it
|
|
* must be zero anyway.
|
|
*/
|
|
div->hw.init = &hw_init;
|
|
div->id = div_init->id;
|
|
div->reg_ctl = div_init->base + CCU_DIV_CTL;
|
|
div->sys_regs = div_init->sys_regs;
|
|
div->flags = div_init->flags;
|
|
div->features = div_init->features;
|
|
spin_lock_init(&div->lock);
|
|
|
|
hw_init.name = div_init->name;
|
|
hw_init.flags = div_init->flags;
|
|
|
|
if (div_init->type == CCU_DIV_VAR) {
|
|
if (hw_init.flags & CLK_SET_RATE_GATE)
|
|
hw_init.ops = &ccu_div_var_gate_to_set_ops;
|
|
else
|
|
hw_init.ops = &ccu_div_var_nogate_ops;
|
|
div->mask = CCU_DIV_CTL_CLKDIV_MASK(div_init->width);
|
|
} else if (div_init->type == CCU_DIV_GATE) {
|
|
hw_init.ops = &ccu_div_gate_ops;
|
|
div->divider = div_init->divider;
|
|
} else if (div_init->type == CCU_DIV_FIXED) {
|
|
hw_init.ops = &ccu_div_fixed_ops;
|
|
div->divider = div_init->divider;
|
|
} else {
|
|
ret = -EINVAL;
|
|
goto err_free_div;
|
|
}
|
|
|
|
if (!div_init->parent_name) {
|
|
ret = -EINVAL;
|
|
goto err_free_div;
|
|
}
|
|
parent_data.fw_name = div_init->parent_name;
|
|
hw_init.parent_data = &parent_data;
|
|
hw_init.num_parents = 1;
|
|
|
|
ret = of_clk_hw_register(div_init->np, &div->hw);
|
|
if (ret)
|
|
goto err_free_div;
|
|
|
|
return div;
|
|
|
|
err_free_div:
|
|
kfree(div);
|
|
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
void ccu_div_hw_unregister(struct ccu_div *div)
|
|
{
|
|
clk_hw_unregister(&div->hw);
|
|
|
|
kfree(div);
|
|
}
|