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![Colin Ian King](/assets/img/avatar_default.png)
There is a spelling mistake in a pr_err error message. Fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20200602121030.39132-1-colin.king@canonical.com Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
485 lines
13 KiB
C
485 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
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*
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* Authors:
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* Serge Semin <Sergey.Semin@baikalelectronics.ru>
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* Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
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*
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* Baikal-T1 CCU Dividers clock driver
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*/
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#define pr_fmt(fmt) "bt1-ccu-div: " fmt
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#include <linux/kernel.h>
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#include <linux/printk.h>
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#include <linux/slab.h>
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#include <linux/clk-provider.h>
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#include <linux/reset-controller.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/ioport.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/bt1-ccu.h>
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#include <dt-bindings/reset/bt1-ccu.h>
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#include "ccu-div.h"
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#define CCU_AXI_MAIN_BASE 0x030
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#define CCU_AXI_DDR_BASE 0x034
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#define CCU_AXI_SATA_BASE 0x038
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#define CCU_AXI_GMAC0_BASE 0x03C
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#define CCU_AXI_GMAC1_BASE 0x040
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#define CCU_AXI_XGMAC_BASE 0x044
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#define CCU_AXI_PCIE_M_BASE 0x048
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#define CCU_AXI_PCIE_S_BASE 0x04C
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#define CCU_AXI_USB_BASE 0x050
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#define CCU_AXI_HWA_BASE 0x054
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#define CCU_AXI_SRAM_BASE 0x058
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#define CCU_SYS_SATA_REF_BASE 0x060
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#define CCU_SYS_APB_BASE 0x064
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#define CCU_SYS_GMAC0_BASE 0x068
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#define CCU_SYS_GMAC1_BASE 0x06C
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#define CCU_SYS_XGMAC_BASE 0x070
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#define CCU_SYS_USB_BASE 0x074
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#define CCU_SYS_PVT_BASE 0x078
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#define CCU_SYS_HWA_BASE 0x07C
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#define CCU_SYS_UART_BASE 0x084
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#define CCU_SYS_TIMER0_BASE 0x088
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#define CCU_SYS_TIMER1_BASE 0x08C
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#define CCU_SYS_TIMER2_BASE 0x090
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#define CCU_SYS_WDT_BASE 0x150
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#define CCU_DIV_VAR_INFO(_id, _name, _pname, _base, _width, _flags, _features) \
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{ \
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.id = _id, \
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.name = _name, \
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.parent_name = _pname, \
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.base = _base, \
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.type = CCU_DIV_VAR, \
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.width = _width, \
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.flags = _flags, \
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.features = _features \
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}
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#define CCU_DIV_GATE_INFO(_id, _name, _pname, _base, _divider) \
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{ \
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.id = _id, \
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.name = _name, \
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.parent_name = _pname, \
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.base = _base, \
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.type = CCU_DIV_GATE, \
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.divider = _divider \
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}
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#define CCU_DIV_FIXED_INFO(_id, _name, _pname, _divider) \
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{ \
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.id = _id, \
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.name = _name, \
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.parent_name = _pname, \
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.type = CCU_DIV_FIXED, \
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.divider = _divider \
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}
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#define CCU_DIV_RST_MAP(_rst_id, _clk_id) \
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{ \
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.rst_id = _rst_id, \
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.clk_id = _clk_id \
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}
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struct ccu_div_info {
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unsigned int id;
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const char *name;
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const char *parent_name;
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unsigned int base;
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enum ccu_div_type type;
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union {
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unsigned int width;
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unsigned int divider;
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};
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unsigned long flags;
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unsigned long features;
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};
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struct ccu_div_rst_map {
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unsigned int rst_id;
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unsigned int clk_id;
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};
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struct ccu_div_data {
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struct device_node *np;
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struct regmap *sys_regs;
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unsigned int divs_num;
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const struct ccu_div_info *divs_info;
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struct ccu_div **divs;
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unsigned int rst_num;
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const struct ccu_div_rst_map *rst_map;
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struct reset_controller_dev rcdev;
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};
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#define to_ccu_div_data(_rcdev) container_of(_rcdev, struct ccu_div_data, rcdev)
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/*
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* AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks
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* must be left enabled in any case, since former one is responsible for
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* clocking a bus between CPU cores and the rest of the SoC components, while
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* the later is clocking the AXI-bus between DDR controller and the Main
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* Interconnect. So should any of these clocks get to be disabled, the system
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* will literally stop working. That's why we marked them as critical.
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*/
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static const struct ccu_div_info axi_info[] = {
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CCU_DIV_VAR_INFO(CCU_AXI_MAIN_CLK, "axi_main_clk", "pcie_clk",
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CCU_AXI_MAIN_BASE, 4,
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CLK_IS_CRITICAL, CCU_DIV_RESET_DOMAIN),
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CCU_DIV_VAR_INFO(CCU_AXI_DDR_CLK, "axi_ddr_clk", "sata_clk",
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CCU_AXI_DDR_BASE, 4,
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CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
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CCU_DIV_RESET_DOMAIN),
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CCU_DIV_VAR_INFO(CCU_AXI_SATA_CLK, "axi_sata_clk", "sata_clk",
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CCU_AXI_SATA_BASE, 4,
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CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
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CCU_DIV_VAR_INFO(CCU_AXI_GMAC0_CLK, "axi_gmac0_clk", "eth_clk",
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CCU_AXI_GMAC0_BASE, 4,
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CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
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CCU_DIV_VAR_INFO(CCU_AXI_GMAC1_CLK, "axi_gmac1_clk", "eth_clk",
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CCU_AXI_GMAC1_BASE, 4,
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CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
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CCU_DIV_VAR_INFO(CCU_AXI_XGMAC_CLK, "axi_xgmac_clk", "eth_clk",
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CCU_AXI_XGMAC_BASE, 4,
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CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
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CCU_DIV_VAR_INFO(CCU_AXI_PCIE_M_CLK, "axi_pcie_m_clk", "pcie_clk",
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CCU_AXI_PCIE_M_BASE, 4,
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CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
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CCU_DIV_VAR_INFO(CCU_AXI_PCIE_S_CLK, "axi_pcie_s_clk", "pcie_clk",
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CCU_AXI_PCIE_S_BASE, 4,
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CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
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CCU_DIV_VAR_INFO(CCU_AXI_USB_CLK, "axi_usb_clk", "sata_clk",
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CCU_AXI_USB_BASE, 4,
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CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
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CCU_DIV_VAR_INFO(CCU_AXI_HWA_CLK, "axi_hwa_clk", "sata_clk",
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CCU_AXI_HWA_BASE, 4,
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CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
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CCU_DIV_VAR_INFO(CCU_AXI_SRAM_CLK, "axi_sram_clk", "eth_clk",
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CCU_AXI_SRAM_BASE, 4,
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CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN)
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};
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static const struct ccu_div_rst_map axi_rst_map[] = {
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CCU_DIV_RST_MAP(CCU_AXI_MAIN_RST, CCU_AXI_MAIN_CLK),
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CCU_DIV_RST_MAP(CCU_AXI_DDR_RST, CCU_AXI_DDR_CLK),
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CCU_DIV_RST_MAP(CCU_AXI_SATA_RST, CCU_AXI_SATA_CLK),
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CCU_DIV_RST_MAP(CCU_AXI_GMAC0_RST, CCU_AXI_GMAC0_CLK),
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CCU_DIV_RST_MAP(CCU_AXI_GMAC1_RST, CCU_AXI_GMAC1_CLK),
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CCU_DIV_RST_MAP(CCU_AXI_XGMAC_RST, CCU_AXI_XGMAC_CLK),
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CCU_DIV_RST_MAP(CCU_AXI_PCIE_M_RST, CCU_AXI_PCIE_M_CLK),
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CCU_DIV_RST_MAP(CCU_AXI_PCIE_S_RST, CCU_AXI_PCIE_S_CLK),
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CCU_DIV_RST_MAP(CCU_AXI_USB_RST, CCU_AXI_USB_CLK),
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CCU_DIV_RST_MAP(CCU_AXI_HWA_RST, CCU_AXI_HWA_CLK),
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CCU_DIV_RST_MAP(CCU_AXI_SRAM_RST, CCU_AXI_SRAM_CLK)
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};
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/*
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* APB-bus clock is marked as critical since it's a main communication bus
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* for the SoC devices registers IO-operations.
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*/
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static const struct ccu_div_info sys_info[] = {
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CCU_DIV_VAR_INFO(CCU_SYS_SATA_REF_CLK, "sys_sata_ref_clk",
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"sata_clk", CCU_SYS_SATA_REF_BASE, 4,
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CLK_SET_RATE_GATE,
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CCU_DIV_SKIP_ONE | CCU_DIV_LOCK_SHIFTED |
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CCU_DIV_RESET_DOMAIN),
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CCU_DIV_VAR_INFO(CCU_SYS_APB_CLK, "sys_apb_clk",
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"pcie_clk", CCU_SYS_APB_BASE, 5,
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CLK_IS_CRITICAL, CCU_DIV_RESET_DOMAIN),
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CCU_DIV_GATE_INFO(CCU_SYS_GMAC0_TX_CLK, "sys_gmac0_tx_clk",
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"eth_clk", CCU_SYS_GMAC0_BASE, 5),
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CCU_DIV_FIXED_INFO(CCU_SYS_GMAC0_PTP_CLK, "sys_gmac0_ptp_clk",
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"eth_clk", 10),
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CCU_DIV_GATE_INFO(CCU_SYS_GMAC1_TX_CLK, "sys_gmac1_tx_clk",
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"eth_clk", CCU_SYS_GMAC1_BASE, 5),
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CCU_DIV_FIXED_INFO(CCU_SYS_GMAC1_PTP_CLK, "sys_gmac1_ptp_clk",
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"eth_clk", 10),
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CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
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"eth_clk", CCU_SYS_XGMAC_BASE, 8),
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CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk",
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"eth_clk", 10),
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CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk",
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"eth_clk", CCU_SYS_USB_BASE, 10),
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CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk",
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"ref_clk", CCU_SYS_PVT_BASE, 5,
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CLK_SET_RATE_GATE, 0),
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CCU_DIV_VAR_INFO(CCU_SYS_HWA_CLK, "sys_hwa_clk",
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"sata_clk", CCU_SYS_HWA_BASE, 4,
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CLK_SET_RATE_GATE, 0),
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CCU_DIV_VAR_INFO(CCU_SYS_UART_CLK, "sys_uart_clk",
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"eth_clk", CCU_SYS_UART_BASE, 17,
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CLK_SET_RATE_GATE, 0),
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CCU_DIV_FIXED_INFO(CCU_SYS_I2C1_CLK, "sys_i2c1_clk",
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"eth_clk", 10),
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CCU_DIV_FIXED_INFO(CCU_SYS_I2C2_CLK, "sys_i2c2_clk",
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"eth_clk", 10),
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CCU_DIV_FIXED_INFO(CCU_SYS_GPIO_CLK, "sys_gpio_clk",
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"ref_clk", 25),
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CCU_DIV_VAR_INFO(CCU_SYS_TIMER0_CLK, "sys_timer0_clk",
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"ref_clk", CCU_SYS_TIMER0_BASE, 17,
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CLK_SET_RATE_GATE, 0),
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CCU_DIV_VAR_INFO(CCU_SYS_TIMER1_CLK, "sys_timer1_clk",
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"ref_clk", CCU_SYS_TIMER1_BASE, 17,
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CLK_SET_RATE_GATE, 0),
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CCU_DIV_VAR_INFO(CCU_SYS_TIMER2_CLK, "sys_timer2_clk",
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"ref_clk", CCU_SYS_TIMER2_BASE, 17,
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CLK_SET_RATE_GATE, 0),
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CCU_DIV_VAR_INFO(CCU_SYS_WDT_CLK, "sys_wdt_clk",
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"eth_clk", CCU_SYS_WDT_BASE, 17,
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CLK_SET_RATE_GATE, CCU_DIV_SKIP_ONE_TO_THREE)
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};
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static const struct ccu_div_rst_map sys_rst_map[] = {
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CCU_DIV_RST_MAP(CCU_SYS_SATA_REF_RST, CCU_SYS_SATA_REF_CLK),
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CCU_DIV_RST_MAP(CCU_SYS_APB_RST, CCU_SYS_APB_CLK),
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};
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static struct ccu_div *ccu_div_find_desc(struct ccu_div_data *data,
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unsigned int clk_id)
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{
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struct ccu_div *div;
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int idx;
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for (idx = 0; idx < data->divs_num; ++idx) {
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div = data->divs[idx];
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if (div && div->id == clk_id)
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return div;
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}
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return ERR_PTR(-EINVAL);
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}
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static int ccu_div_reset(struct reset_controller_dev *rcdev,
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unsigned long rst_id)
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{
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struct ccu_div_data *data = to_ccu_div_data(rcdev);
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const struct ccu_div_rst_map *map;
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struct ccu_div *div;
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int idx, ret;
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for (idx = 0, map = data->rst_map; idx < data->rst_num; ++idx, ++map) {
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if (map->rst_id == rst_id)
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break;
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}
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if (idx == data->rst_num) {
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pr_err("Invalid reset ID %lu specified\n", rst_id);
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return -EINVAL;
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}
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div = ccu_div_find_desc(data, map->clk_id);
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if (IS_ERR(div)) {
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pr_err("Invalid clock ID %d in mapping\n", map->clk_id);
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return PTR_ERR(div);
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}
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ret = ccu_div_reset_domain(div);
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if (ret) {
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pr_err("Reset isn't supported by divider %s\n",
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clk_hw_get_name(ccu_div_get_clk_hw(div)));
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}
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return ret;
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}
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static const struct reset_control_ops ccu_div_rst_ops = {
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.reset = ccu_div_reset,
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};
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static struct ccu_div_data *ccu_div_create_data(struct device_node *np)
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{
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struct ccu_div_data *data;
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int ret;
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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return ERR_PTR(-ENOMEM);
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data->np = np;
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if (of_device_is_compatible(np, "baikal,bt1-ccu-axi")) {
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data->divs_num = ARRAY_SIZE(axi_info);
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data->divs_info = axi_info;
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data->rst_num = ARRAY_SIZE(axi_rst_map);
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data->rst_map = axi_rst_map;
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} else if (of_device_is_compatible(np, "baikal,bt1-ccu-sys")) {
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data->divs_num = ARRAY_SIZE(sys_info);
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data->divs_info = sys_info;
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data->rst_num = ARRAY_SIZE(sys_rst_map);
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data->rst_map = sys_rst_map;
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} else {
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pr_err("Incompatible DT node '%s' specified\n",
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of_node_full_name(np));
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ret = -EINVAL;
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goto err_kfree_data;
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}
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data->divs = kcalloc(data->divs_num, sizeof(*data->divs), GFP_KERNEL);
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if (!data->divs) {
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ret = -ENOMEM;
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goto err_kfree_data;
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}
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return data;
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err_kfree_data:
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kfree(data);
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return ERR_PTR(ret);
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}
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static void ccu_div_free_data(struct ccu_div_data *data)
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{
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kfree(data->divs);
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kfree(data);
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}
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static int ccu_div_find_sys_regs(struct ccu_div_data *data)
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{
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data->sys_regs = syscon_node_to_regmap(data->np->parent);
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if (IS_ERR(data->sys_regs)) {
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pr_err("Failed to find syscon regs for '%s'\n",
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of_node_full_name(data->np));
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return PTR_ERR(data->sys_regs);
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}
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return 0;
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}
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static struct clk_hw *ccu_div_of_clk_hw_get(struct of_phandle_args *clkspec,
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void *priv)
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{
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struct ccu_div_data *data = priv;
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struct ccu_div *div;
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unsigned int clk_id;
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clk_id = clkspec->args[0];
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div = ccu_div_find_desc(data, clk_id);
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if (IS_ERR(div)) {
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pr_info("Invalid clock ID %d specified\n", clk_id);
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return ERR_CAST(div);
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}
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return ccu_div_get_clk_hw(div);
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}
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static int ccu_div_clk_register(struct ccu_div_data *data)
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{
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int idx, ret;
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for (idx = 0; idx < data->divs_num; ++idx) {
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const struct ccu_div_info *info = &data->divs_info[idx];
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struct ccu_div_init_data init = {0};
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init.id = info->id;
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init.name = info->name;
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init.parent_name = info->parent_name;
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init.np = data->np;
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init.type = info->type;
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init.flags = info->flags;
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init.features = info->features;
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if (init.type == CCU_DIV_VAR) {
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init.base = info->base;
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init.sys_regs = data->sys_regs;
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init.width = info->width;
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} else if (init.type == CCU_DIV_GATE) {
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init.base = info->base;
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init.sys_regs = data->sys_regs;
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init.divider = info->divider;
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} else {
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init.divider = info->divider;
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}
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data->divs[idx] = ccu_div_hw_register(&init);
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if (IS_ERR(data->divs[idx])) {
|
|
ret = PTR_ERR(data->divs[idx]);
|
|
pr_err("Couldn't register divider '%s' hw\n",
|
|
init.name);
|
|
goto err_hw_unregister;
|
|
}
|
|
}
|
|
|
|
ret = of_clk_add_hw_provider(data->np, ccu_div_of_clk_hw_get, data);
|
|
if (ret) {
|
|
pr_err("Couldn't register dividers '%s' clock provider\n",
|
|
of_node_full_name(data->np));
|
|
goto err_hw_unregister;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_hw_unregister:
|
|
for (--idx; idx >= 0; --idx)
|
|
ccu_div_hw_unregister(data->divs[idx]);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void ccu_div_clk_unregister(struct ccu_div_data *data)
|
|
{
|
|
int idx;
|
|
|
|
of_clk_del_provider(data->np);
|
|
|
|
for (idx = 0; idx < data->divs_num; ++idx)
|
|
ccu_div_hw_unregister(data->divs[idx]);
|
|
}
|
|
|
|
static int ccu_div_rst_register(struct ccu_div_data *data)
|
|
{
|
|
int ret;
|
|
|
|
data->rcdev.ops = &ccu_div_rst_ops;
|
|
data->rcdev.of_node = data->np;
|
|
data->rcdev.nr_resets = data->rst_num;
|
|
|
|
ret = reset_controller_register(&data->rcdev);
|
|
if (ret)
|
|
pr_err("Couldn't register divider '%s' reset controller\n",
|
|
of_node_full_name(data->np));
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void ccu_div_init(struct device_node *np)
|
|
{
|
|
struct ccu_div_data *data;
|
|
int ret;
|
|
|
|
data = ccu_div_create_data(np);
|
|
if (IS_ERR(data))
|
|
return;
|
|
|
|
ret = ccu_div_find_sys_regs(data);
|
|
if (ret)
|
|
goto err_free_data;
|
|
|
|
ret = ccu_div_clk_register(data);
|
|
if (ret)
|
|
goto err_free_data;
|
|
|
|
ret = ccu_div_rst_register(data);
|
|
if (ret)
|
|
goto err_clk_unregister;
|
|
|
|
return;
|
|
|
|
err_clk_unregister:
|
|
ccu_div_clk_unregister(data);
|
|
|
|
err_free_data:
|
|
ccu_div_free_data(data);
|
|
}
|
|
|
|
CLK_OF_DECLARE(ccu_axi, "baikal,bt1-ccu-axi", ccu_div_init);
|
|
CLK_OF_DECLARE(ccu_sys, "baikal,bt1-ccu-sys", ccu_div_init);
|