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6f2e120824
Add MT8186 camsys clock controllers which provide clock gate control for camera IP blocks. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-14-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
90 lines
2.7 KiB
C
90 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright (c) 2022 MediaTek Inc.
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// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/mt8186-clk.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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static const struct mtk_gate_regs cam_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_CAM(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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static const struct mtk_gate cam_clks[] = {
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GATE_CAM(CLK_CAM_LARB13, "cam_larb13", "top_cam", 0),
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GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "top_cam", 1),
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GATE_CAM(CLK_CAM_LARB14, "cam_larb14", "top_cam", 2),
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GATE_CAM(CLK_CAM, "cam", "top_cam", 6),
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GATE_CAM(CLK_CAMTG, "camtg", "top_cam", 7),
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GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "top_cam", 8),
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GATE_CAM(CLK_CAMSV1, "camsv1", "top_cam", 10),
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GATE_CAM(CLK_CAMSV2, "camsv2", "top_cam", 11),
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GATE_CAM(CLK_CAMSV3, "camsv3", "top_cam", 12),
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GATE_CAM(CLK_CAM_CCU0, "cam_ccu0", "top_cam", 13),
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GATE_CAM(CLK_CAM_CCU1, "cam_ccu1", "top_cam", 14),
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GATE_CAM(CLK_CAM_MRAW0, "cam_mraw0", "top_cam", 15),
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GATE_CAM(CLK_CAM_FAKE_ENG, "cam_fake_eng", "top_cam", 17),
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GATE_CAM(CLK_CAM_CCU_GALS, "cam_ccu_gals", "top_cam", 18),
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GATE_CAM(CLK_CAM2MM_GALS, "cam2mm_gals", "top_cam", 19),
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};
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static const struct mtk_gate cam_rawa_clks[] = {
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GATE_CAM(CLK_CAM_RAWA_LARBX_RAWA, "cam_rawa_larbx_rawa", "top_cam", 0),
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GATE_CAM(CLK_CAM_RAWA, "cam_rawa", "top_cam", 1),
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GATE_CAM(CLK_CAM_RAWA_CAMTG_RAWA, "cam_rawa_camtg_rawa", "top_cam", 2),
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};
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static const struct mtk_gate cam_rawb_clks[] = {
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GATE_CAM(CLK_CAM_RAWB_LARBX_RAWB, "cam_rawb_larbx_rawb", "top_cam", 0),
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GATE_CAM(CLK_CAM_RAWB, "cam_rawb", "top_cam", 1),
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GATE_CAM(CLK_CAM_RAWB_CAMTG_RAWB, "cam_rawb_camtg_rawb", "top_cam", 2),
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};
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static const struct mtk_clk_desc cam_desc = {
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.clks = cam_clks,
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.num_clks = ARRAY_SIZE(cam_clks),
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};
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static const struct mtk_clk_desc cam_rawa_desc = {
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.clks = cam_rawa_clks,
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.num_clks = ARRAY_SIZE(cam_rawa_clks),
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};
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static const struct mtk_clk_desc cam_rawb_desc = {
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.clks = cam_rawb_clks,
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.num_clks = ARRAY_SIZE(cam_rawb_clks),
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};
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static const struct of_device_id of_match_clk_mt8186_cam[] = {
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{
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.compatible = "mediatek,mt8186-camsys",
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.data = &cam_desc,
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}, {
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.compatible = "mediatek,mt8186-camsys_rawa",
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.data = &cam_rawa_desc,
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}, {
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.compatible = "mediatek,mt8186-camsys_rawb",
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.data = &cam_rawb_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt8186_cam_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8186-cam",
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.of_match_table = of_match_clk_mt8186_cam,
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},
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};
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builtin_platform_driver(clk_mt8186_cam_drv);
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