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a677bdf8b6
Add MT8186 ipesys clock controller which provides clock gate control for Image Process Engine. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-16-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
55 lines
1.5 KiB
C
55 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright (c) 2022 MediaTek Inc.
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// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/mt8186-clk.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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static const struct mtk_gate_regs ipe_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_IPE(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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static const struct mtk_gate ipe_clks[] = {
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GATE_IPE(CLK_IPE_LARB19, "ipe_larb19", "top_ipe", 0),
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GATE_IPE(CLK_IPE_LARB20, "ipe_larb20", "top_ipe", 1),
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GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "top_ipe", 2),
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GATE_IPE(CLK_IPE_FD, "ipe_fd", "top_ipe", 3),
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GATE_IPE(CLK_IPE_FE, "ipe_fe", "top_ipe", 4),
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GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "top_ipe", 5),
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GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 6),
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GATE_IPE(CLK_IPE_GALS_IPE, "ipe_gals_ipe", "top_img1", 8),
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};
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static const struct mtk_clk_desc ipe_desc = {
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.clks = ipe_clks,
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.num_clks = ARRAY_SIZE(ipe_clks),
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};
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static const struct of_device_id of_match_clk_mt8186_ipe[] = {
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{
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.compatible = "mediatek,mt8186-ipesys",
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.data = &ipe_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt8186_ipe_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8186-ipe",
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.of_match_table = of_match_clk_mt8186_ipe,
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},
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};
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builtin_platform_driver(clk_mt8186_ipe_drv);
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