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![Chen-Yu Tsai](/assets/img/avatar_default.png)
As part of the effort to improve the MediaTek clk drivers, the next step is to switch from the old 'struct clk' clk prodivder APIs to the new 'struct clk_hw' ones. In a previous patch, 'struct clk_onecell_data' was replaced with 'struct clk_hw_onecell_data', with (struct clk_hw *)->clk and __clk_get_hw() bridging the new data structures and old code. Now switch from the old 'clk_(un)?register*()' APIs to the new 'clk_hw_(un)?register*()' ones. This is done with the coccinelle script below. Unfortunately this also leaves clk-mt8173.c with a compile error that would need a coccinelle script longer than the actual diff to fix. This last part is fixed up by hand. // Fix prototypes @@ identifier F =~ "^mtk_clk_register_"; @@ - struct clk * + struct clk_hw * F(...); // Fix calls to mtk_clk_register_<singular> @ reg @ identifier F =~ "^mtk_clk_register_"; identifier FS =~ "^mtk_clk_register_[a-z_]*s"; identifier I; expression clk_data; expression E; @@ FS(...) { ... - struct clk *I; + struct clk_hw *hw; ... for (...;...;...) { ... ( - I + hw = - clk_register_fixed_rate( + clk_hw_register_fixed_rate( ... ); | - I + hw = - clk_register_fixed_factor( + clk_hw_register_fixed_factor( ... ); | - I + hw = - clk_register_divider( + clk_hw_register_divider( ... ); | - I + hw = F(...); ) ... if ( - IS_ERR(I) + IS_ERR(hw) ) { pr_err(..., - I + hw ,...); ... } - clk_data->hws[E] = __clk_get_hw(I); + clk_data->hws[E] = hw; } ... } @ depends on reg @ identifier reg.I; @@ return PTR_ERR( - I + hw ); // Fix mtk_clk_register_composite to return clk_hw instead of clk @@ identifier I, R; expression E; @@ - struct clk * + struct clk_hw * mtk_clk_register_composite(...) { ... - struct clk *I; + struct clk_hw *hw; ... - I = clk_register_composite( + hw = clk_hw_register_composite( ...); if (IS_ERR( - I + hw )) { ... R = PTR_ERR( - I + hw ); ... } return - I + hw ; ... } // Fix other mtk_clk_register_<singular> to return clk_hw instead of clk @@ identifier F =~ "^mtk_clk_register_"; identifier I, D, C; expression E; @@ - struct clk * + struct clk_hw * F(...) { ... - struct clk *I; + int ret; ... - I = clk_register(D, E); + ret = clk_hw_register(D, E); ... ( - if (IS_ERR(I)) + if (ret) { kfree(C); + return ERR_PTR(ret); + } | - if (IS_ERR(I)) + if (ret) { kfree(C); - return I; + return ERR_PTR(ret); } ) - return I; + return E; } // Fix mtk_clk_unregister_<singular> to take clk_hw instead of clk @@ identifier F =~ "^mtk_clk_unregister_"; identifier I, I2; @@ static void F( - struct clk *I + struct clk_hw *I2 ) { ... - struct clk_hw *I2; ... - I2 = __clk_get_hw(I); ... ( - clk_unregister(I); + clk_hw_unregister(I2); | - clk_unregister_composite(I); + clk_hw_unregister_composite(I2); ) ... } // Fix calls to mtk_clk_unregister_*() @@ identifier F =~ "^mtk_clk_unregister_"; expression I; expression E; @@ - F(I->hws[E]->clk); + F(I->hws[E]); Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220519071610.423372-5-wenst@chromium.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
204 lines
5.3 KiB
C
204 lines
5.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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*/
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#ifndef __DRV_CLK_MTK_H
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#define __DRV_CLK_MTK_H
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#define MAX_MUX_GATE_BIT 31
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#define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
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#define MHZ (1000 * 1000)
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struct platform_device;
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struct mtk_fixed_clk {
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int id;
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const char *name;
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const char *parent;
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unsigned long rate;
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};
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#define FIXED_CLK(_id, _name, _parent, _rate) { \
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.id = _id, \
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.name = _name, \
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.parent = _parent, \
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.rate = _rate, \
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}
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int mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num,
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struct clk_hw_onecell_data *clk_data);
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void mtk_clk_unregister_fixed_clks(const struct mtk_fixed_clk *clks, int num,
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struct clk_hw_onecell_data *clk_data);
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struct mtk_fixed_factor {
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int id;
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const char *name;
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const char *parent_name;
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int mult;
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int div;
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};
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#define FACTOR(_id, _name, _parent, _mult, _div) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.mult = _mult, \
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.div = _div, \
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}
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int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
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struct clk_hw_onecell_data *clk_data);
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void mtk_clk_unregister_factors(const struct mtk_fixed_factor *clks, int num,
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struct clk_hw_onecell_data *clk_data);
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struct mtk_composite {
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int id;
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const char *name;
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const char * const *parent_names;
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const char *parent;
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unsigned flags;
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uint32_t mux_reg;
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uint32_t divider_reg;
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uint32_t gate_reg;
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signed char mux_shift;
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signed char mux_width;
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signed char gate_shift;
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signed char divider_shift;
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signed char divider_width;
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u8 mux_flags;
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signed char num_parents;
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};
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#define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \
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_width, _gate, _flags, _muxflags) { \
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.id = _id, \
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.name = _name, \
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.mux_reg = _reg, \
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.mux_shift = _shift, \
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.mux_width = _width, \
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.gate_reg = _reg, \
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.gate_shift = _gate, \
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.divider_shift = -1, \
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.parent_names = _parents, \
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.num_parents = ARRAY_SIZE(_parents), \
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.flags = _flags, \
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.mux_flags = _muxflags, \
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}
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/*
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* In case the rate change propagation to parent clocks is undesirable,
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* this macro allows to specify the clock flags manually.
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*/
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#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
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_gate, _flags) \
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MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \
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_shift, _width, _gate, _flags, 0)
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/*
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* Unless necessary, all MUX_GATE clocks propagate rate changes to their
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* parent clock by default.
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*/
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#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \
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MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
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_gate, CLK_SET_RATE_PARENT)
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#define MUX(_id, _name, _parents, _reg, _shift, _width) \
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MUX_FLAGS(_id, _name, _parents, _reg, \
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_shift, _width, CLK_SET_RATE_PARENT)
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#define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \
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.id = _id, \
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.name = _name, \
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.mux_reg = _reg, \
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.mux_shift = _shift, \
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.mux_width = _width, \
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.gate_shift = -1, \
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.divider_shift = -1, \
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.parent_names = _parents, \
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.num_parents = ARRAY_SIZE(_parents), \
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.flags = _flags, \
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}
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#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
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_div_width, _div_shift) { \
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.id = _id, \
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.parent = _parent, \
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.name = _name, \
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.divider_reg = _div_reg, \
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.divider_shift = _div_shift, \
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.divider_width = _div_width, \
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.gate_reg = _gate_reg, \
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.gate_shift = _gate_shift, \
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.mux_shift = -1, \
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.flags = 0, \
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}
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int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
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void __iomem *base, spinlock_t *lock,
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struct clk_hw_onecell_data *clk_data);
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void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num,
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struct clk_hw_onecell_data *clk_data);
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struct mtk_clk_divider {
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int id;
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const char *name;
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const char *parent_name;
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unsigned long flags;
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u32 div_reg;
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unsigned char div_shift;
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unsigned char div_width;
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unsigned char clk_divider_flags;
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const struct clk_div_table *clk_div_table;
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};
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#define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.div_reg = _reg, \
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.div_shift = _shift, \
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.div_width = _width, \
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}
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int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num,
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void __iomem *base, spinlock_t *lock,
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struct clk_hw_onecell_data *clk_data);
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void mtk_clk_unregister_dividers(const struct mtk_clk_divider *mcds, int num,
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struct clk_hw_onecell_data *clk_data);
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struct clk_hw_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
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void mtk_free_clk_data(struct clk_hw_onecell_data *clk_data);
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struct clk_hw *mtk_clk_register_ref2usb_tx(const char *name,
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const char *parent_name, void __iomem *reg);
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void mtk_register_reset_controller(struct device_node *np,
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unsigned int num_regs, int regofs);
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void mtk_register_reset_controller_set_clr(struct device_node *np,
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unsigned int num_regs, int regofs);
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struct mtk_clk_desc {
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const struct mtk_gate *clks;
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size_t num_clks;
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};
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int mtk_clk_simple_probe(struct platform_device *pdev);
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int mtk_clk_simple_remove(struct platform_device *pdev);
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#endif /* __DRV_CLK_MTK_H */
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