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![Chen-Yu Tsai](/assets/img/avatar_default.png)
As part of the effort to improve the MediaTek clk drivers, the next step is to switch from the old 'struct clk' clk prodivder APIs to the new 'struct clk_hw' ones. In a previous patch, 'struct clk_onecell_data' was replaced with 'struct clk_hw_onecell_data', with (struct clk_hw *)->clk and __clk_get_hw() bridging the new data structures and old code. Now switch from the old 'clk_(un)?register*()' APIs to the new 'clk_hw_(un)?register*()' ones. This is done with the coccinelle script below. Unfortunately this also leaves clk-mt8173.c with a compile error that would need a coccinelle script longer than the actual diff to fix. This last part is fixed up by hand. // Fix prototypes @@ identifier F =~ "^mtk_clk_register_"; @@ - struct clk * + struct clk_hw * F(...); // Fix calls to mtk_clk_register_<singular> @ reg @ identifier F =~ "^mtk_clk_register_"; identifier FS =~ "^mtk_clk_register_[a-z_]*s"; identifier I; expression clk_data; expression E; @@ FS(...) { ... - struct clk *I; + struct clk_hw *hw; ... for (...;...;...) { ... ( - I + hw = - clk_register_fixed_rate( + clk_hw_register_fixed_rate( ... ); | - I + hw = - clk_register_fixed_factor( + clk_hw_register_fixed_factor( ... ); | - I + hw = - clk_register_divider( + clk_hw_register_divider( ... ); | - I + hw = F(...); ) ... if ( - IS_ERR(I) + IS_ERR(hw) ) { pr_err(..., - I + hw ,...); ... } - clk_data->hws[E] = __clk_get_hw(I); + clk_data->hws[E] = hw; } ... } @ depends on reg @ identifier reg.I; @@ return PTR_ERR( - I + hw ); // Fix mtk_clk_register_composite to return clk_hw instead of clk @@ identifier I, R; expression E; @@ - struct clk * + struct clk_hw * mtk_clk_register_composite(...) { ... - struct clk *I; + struct clk_hw *hw; ... - I = clk_register_composite( + hw = clk_hw_register_composite( ...); if (IS_ERR( - I + hw )) { ... R = PTR_ERR( - I + hw ); ... } return - I + hw ; ... } // Fix other mtk_clk_register_<singular> to return clk_hw instead of clk @@ identifier F =~ "^mtk_clk_register_"; identifier I, D, C; expression E; @@ - struct clk * + struct clk_hw * F(...) { ... - struct clk *I; + int ret; ... - I = clk_register(D, E); + ret = clk_hw_register(D, E); ... ( - if (IS_ERR(I)) + if (ret) { kfree(C); + return ERR_PTR(ret); + } | - if (IS_ERR(I)) + if (ret) { kfree(C); - return I; + return ERR_PTR(ret); } ) - return I; + return E; } // Fix mtk_clk_unregister_<singular> to take clk_hw instead of clk @@ identifier F =~ "^mtk_clk_unregister_"; identifier I, I2; @@ static void F( - struct clk *I + struct clk_hw *I2 ) { ... - struct clk_hw *I2; ... - I2 = __clk_get_hw(I); ... ( - clk_unregister(I); + clk_hw_unregister(I2); | - clk_unregister_composite(I); + clk_hw_unregister_composite(I2); ) ... } // Fix calls to mtk_clk_unregister_*() @@ identifier F =~ "^mtk_clk_unregister_"; expression I; expression E; @@ - F(I->hws[E]->clk); + F(I->hws[E]); Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220519071610.423372-5-wenst@chromium.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
262 lines
5.7 KiB
C
262 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Owen Chen <owen.chen@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/compiler_types.h>
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#include <linux/container_of.h>
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#include <linux/err.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include "clk-mux.h"
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struct mtk_clk_mux {
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struct clk_hw hw;
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struct regmap *regmap;
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const struct mtk_mux *data;
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spinlock_t *lock;
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bool reparent;
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};
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static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
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{
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return container_of(hw, struct mtk_clk_mux, hw);
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}
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static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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unsigned long flags = 0;
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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else
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__acquire(mux->lock);
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regmap_write(mux->regmap, mux->data->clr_ofs,
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BIT(mux->data->gate_shift));
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/*
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* If the parent has been changed when the clock was disabled, it will
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* not be effective yet. Set the update bit to ensure the mux gets
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* updated.
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*/
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if (mux->reparent && mux->data->upd_shift >= 0) {
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regmap_write(mux->regmap, mux->data->upd_ofs,
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BIT(mux->data->upd_shift));
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mux->reparent = false;
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}
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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else
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__release(mux->lock);
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return 0;
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}
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static void mtk_clk_mux_disable_setclr(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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regmap_write(mux->regmap, mux->data->set_ofs,
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BIT(mux->data->gate_shift));
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}
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static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 val;
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regmap_read(mux->regmap, mux->data->mux_ofs, &val);
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return (val & BIT(mux->data->gate_shift)) == 0;
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}
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static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 mask = GENMASK(mux->data->mux_width - 1, 0);
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u32 val;
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regmap_read(mux->regmap, mux->data->mux_ofs, &val);
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val = (val >> mux->data->mux_shift) & mask;
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return val;
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}
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static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
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{
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struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
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u32 mask = GENMASK(mux->data->mux_width - 1, 0);
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u32 val, orig;
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unsigned long flags = 0;
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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else
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__acquire(mux->lock);
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regmap_read(mux->regmap, mux->data->mux_ofs, &orig);
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val = (orig & ~(mask << mux->data->mux_shift))
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| (index << mux->data->mux_shift);
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if (val != orig) {
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regmap_write(mux->regmap, mux->data->clr_ofs,
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mask << mux->data->mux_shift);
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regmap_write(mux->regmap, mux->data->set_ofs,
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index << mux->data->mux_shift);
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if (mux->data->upd_shift >= 0) {
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regmap_write(mux->regmap, mux->data->upd_ofs,
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BIT(mux->data->upd_shift));
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mux->reparent = true;
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}
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}
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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else
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__release(mux->lock);
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return 0;
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}
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const struct clk_ops mtk_mux_clr_set_upd_ops = {
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.get_parent = mtk_clk_mux_get_parent,
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.set_parent = mtk_clk_mux_set_parent_setclr_lock,
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};
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EXPORT_SYMBOL_GPL(mtk_mux_clr_set_upd_ops);
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const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
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.enable = mtk_clk_mux_enable_setclr,
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.disable = mtk_clk_mux_disable_setclr,
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.is_enabled = mtk_clk_mux_is_enabled,
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.get_parent = mtk_clk_mux_get_parent,
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.set_parent = mtk_clk_mux_set_parent_setclr_lock,
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};
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EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
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static struct clk_hw *mtk_clk_register_mux(const struct mtk_mux *mux,
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struct regmap *regmap,
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spinlock_t *lock)
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{
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struct mtk_clk_mux *clk_mux;
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struct clk_init_data init = {};
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int ret;
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clk_mux = kzalloc(sizeof(*clk_mux), GFP_KERNEL);
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if (!clk_mux)
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return ERR_PTR(-ENOMEM);
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init.name = mux->name;
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init.flags = mux->flags | CLK_SET_RATE_PARENT;
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init.parent_names = mux->parent_names;
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init.num_parents = mux->num_parents;
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init.ops = mux->ops;
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clk_mux->regmap = regmap;
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clk_mux->data = mux;
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clk_mux->lock = lock;
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clk_mux->hw.init = &init;
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ret = clk_hw_register(NULL, &clk_mux->hw);
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if (ret) {
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kfree(clk_mux);
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return ERR_PTR(ret);
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}
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return &clk_mux->hw;
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}
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static void mtk_clk_unregister_mux(struct clk_hw *hw)
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{
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struct mtk_clk_mux *mux;
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if (!hw)
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return;
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mux = to_mtk_clk_mux(hw);
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clk_hw_unregister(hw);
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kfree(mux);
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}
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int mtk_clk_register_muxes(const struct mtk_mux *muxes,
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int num, struct device_node *node,
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spinlock_t *lock,
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struct clk_hw_onecell_data *clk_data)
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{
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struct regmap *regmap;
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struct clk_hw *hw;
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int i;
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regmap = device_node_to_regmap(node);
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if (IS_ERR(regmap)) {
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pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap);
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return PTR_ERR(regmap);
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}
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for (i = 0; i < num; i++) {
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const struct mtk_mux *mux = &muxes[i];
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if (!IS_ERR_OR_NULL(clk_data->hws[mux->id])) {
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pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
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node, mux->id);
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continue;
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}
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hw = mtk_clk_register_mux(mux, regmap, lock);
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if (IS_ERR(hw)) {
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pr_err("Failed to register clk %s: %pe\n", mux->name,
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hw);
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goto err;
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}
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clk_data->hws[mux->id] = hw;
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}
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return 0;
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err:
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while (--i >= 0) {
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const struct mtk_mux *mux = &muxes[i];
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if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))
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continue;
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mtk_clk_unregister_mux(clk_data->hws[mux->id]);
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clk_data->hws[mux->id] = ERR_PTR(-ENOENT);
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}
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return PTR_ERR(hw);
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}
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EXPORT_SYMBOL_GPL(mtk_clk_register_muxes);
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void mtk_clk_unregister_muxes(const struct mtk_mux *muxes, int num,
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struct clk_hw_onecell_data *clk_data)
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{
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int i;
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if (!clk_data)
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return;
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for (i = num; i > 0; i--) {
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const struct mtk_mux *mux = &muxes[i - 1];
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if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))
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continue;
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mtk_clk_unregister_mux(clk_data->hws[mux->id]);
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clk_data->hws[mux->id] = ERR_PTR(-ENOENT);
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}
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}
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EXPORT_SYMBOL_GPL(mtk_clk_unregister_muxes);
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MODULE_LICENSE("GPL");
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