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![Chen-Yu Tsai](/assets/img/avatar_default.png)
As part of the effort to improve the MediaTek clk drivers, the next step is to switch from the old 'struct clk' clk prodivder APIs to the new 'struct clk_hw' ones. In a previous patch, 'struct clk_onecell_data' was replaced with 'struct clk_hw_onecell_data', with (struct clk_hw *)->clk and __clk_get_hw() bridging the new data structures and old code. Now switch from the old 'clk_(un)?register*()' APIs to the new 'clk_hw_(un)?register*()' ones. This is done with the coccinelle script below. Unfortunately this also leaves clk-mt8173.c with a compile error that would need a coccinelle script longer than the actual diff to fix. This last part is fixed up by hand. // Fix prototypes @@ identifier F =~ "^mtk_clk_register_"; @@ - struct clk * + struct clk_hw * F(...); // Fix calls to mtk_clk_register_<singular> @ reg @ identifier F =~ "^mtk_clk_register_"; identifier FS =~ "^mtk_clk_register_[a-z_]*s"; identifier I; expression clk_data; expression E; @@ FS(...) { ... - struct clk *I; + struct clk_hw *hw; ... for (...;...;...) { ... ( - I + hw = - clk_register_fixed_rate( + clk_hw_register_fixed_rate( ... ); | - I + hw = - clk_register_fixed_factor( + clk_hw_register_fixed_factor( ... ); | - I + hw = - clk_register_divider( + clk_hw_register_divider( ... ); | - I + hw = F(...); ) ... if ( - IS_ERR(I) + IS_ERR(hw) ) { pr_err(..., - I + hw ,...); ... } - clk_data->hws[E] = __clk_get_hw(I); + clk_data->hws[E] = hw; } ... } @ depends on reg @ identifier reg.I; @@ return PTR_ERR( - I + hw ); // Fix mtk_clk_register_composite to return clk_hw instead of clk @@ identifier I, R; expression E; @@ - struct clk * + struct clk_hw * mtk_clk_register_composite(...) { ... - struct clk *I; + struct clk_hw *hw; ... - I = clk_register_composite( + hw = clk_hw_register_composite( ...); if (IS_ERR( - I + hw )) { ... R = PTR_ERR( - I + hw ); ... } return - I + hw ; ... } // Fix other mtk_clk_register_<singular> to return clk_hw instead of clk @@ identifier F =~ "^mtk_clk_register_"; identifier I, D, C; expression E; @@ - struct clk * + struct clk_hw * F(...) { ... - struct clk *I; + int ret; ... - I = clk_register(D, E); + ret = clk_hw_register(D, E); ... ( - if (IS_ERR(I)) + if (ret) { kfree(C); + return ERR_PTR(ret); + } | - if (IS_ERR(I)) + if (ret) { kfree(C); - return I; + return ERR_PTR(ret); } ) - return I; + return E; } // Fix mtk_clk_unregister_<singular> to take clk_hw instead of clk @@ identifier F =~ "^mtk_clk_unregister_"; identifier I, I2; @@ static void F( - struct clk *I + struct clk_hw *I2 ) { ... - struct clk_hw *I2; ... - I2 = __clk_get_hw(I); ... ( - clk_unregister(I); + clk_hw_unregister(I2); | - clk_unregister_composite(I); + clk_hw_unregister_composite(I2); ) ... } // Fix calls to mtk_clk_unregister_*() @@ identifier F =~ "^mtk_clk_unregister_"; expression I; expression E; @@ - F(I->hws[E]->clk); + F(I->hws[E]); Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220519071610.423372-5-wenst@chromium.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
465 lines
10 KiB
C
465 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/container_of.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include "clk-pll.h"
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#define MHZ (1000 * 1000)
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#define REG_CON0 0
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#define REG_CON1 4
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#define CON0_BASE_EN BIT(0)
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#define CON0_PWR_ON BIT(0)
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#define CON0_ISO_EN BIT(1)
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#define PCW_CHG_MASK BIT(31)
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#define AUDPLL_TUNER_EN BIT(31)
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#define POSTDIV_MASK 0x7
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/* default 7 bits integer, can be overridden with pcwibits. */
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#define INTEGER_BITS 7
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/*
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* MediaTek PLLs are configured through their pcw value. The pcw value describes
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* a divider in the PLL feedback loop which consists of 7 bits for the integer
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* part and the remaining bits (if present) for the fractional part. Also they
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* have a 3 bit power-of-two post divider.
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*/
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struct mtk_clk_pll {
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struct clk_hw hw;
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void __iomem *base_addr;
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void __iomem *pd_addr;
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void __iomem *pwr_addr;
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void __iomem *tuner_addr;
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void __iomem *tuner_en_addr;
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void __iomem *pcw_addr;
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void __iomem *pcw_chg_addr;
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void __iomem *en_addr;
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const struct mtk_pll_data *data;
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};
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static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
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{
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return container_of(hw, struct mtk_clk_pll, hw);
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}
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static int mtk_pll_is_prepared(struct clk_hw *hw)
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{
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struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
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return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
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}
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static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
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u32 pcw, int postdiv)
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{
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int pcwbits = pll->data->pcwbits;
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int pcwfbits = 0;
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int ibits;
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u64 vco;
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u8 c = 0;
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/* The fractional part of the PLL divider. */
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ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
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if (pcwbits > ibits)
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pcwfbits = pcwbits - ibits;
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vco = (u64)fin * pcw;
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if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
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c = 1;
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vco >>= pcwfbits;
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if (c)
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vco++;
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return ((unsigned long)vco + postdiv - 1) / postdiv;
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}
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static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
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{
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u32 r;
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if (pll->tuner_en_addr) {
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r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
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writel(r, pll->tuner_en_addr);
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} else if (pll->tuner_addr) {
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r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
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writel(r, pll->tuner_addr);
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}
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}
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static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
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{
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u32 r;
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if (pll->tuner_en_addr) {
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r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
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writel(r, pll->tuner_en_addr);
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} else if (pll->tuner_addr) {
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r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
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writel(r, pll->tuner_addr);
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}
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}
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static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
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int postdiv)
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{
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u32 chg, val;
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/* disable tuner */
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__mtk_pll_tuner_disable(pll);
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/* set postdiv */
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val = readl(pll->pd_addr);
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val &= ~(POSTDIV_MASK << pll->data->pd_shift);
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val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
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/* postdiv and pcw need to set at the same time if on same register */
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if (pll->pd_addr != pll->pcw_addr) {
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writel(val, pll->pd_addr);
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val = readl(pll->pcw_addr);
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}
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/* set pcw */
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val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
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pll->data->pcw_shift);
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val |= pcw << pll->data->pcw_shift;
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writel(val, pll->pcw_addr);
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chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
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writel(chg, pll->pcw_chg_addr);
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if (pll->tuner_addr)
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writel(val + 1, pll->tuner_addr);
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/* restore tuner_en */
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__mtk_pll_tuner_enable(pll);
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udelay(20);
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}
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/*
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* mtk_pll_calc_values - calculate good values for a given input frequency.
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* @pll: The pll
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* @pcw: The pcw value (output)
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* @postdiv: The post divider (output)
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* @freq: The desired target frequency
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* @fin: The input frequency
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*
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*/
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static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
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u32 freq, u32 fin)
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{
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unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
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const struct mtk_pll_div_table *div_table = pll->data->div_table;
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u64 _pcw;
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int ibits;
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u32 val;
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if (freq > pll->data->fmax)
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freq = pll->data->fmax;
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if (div_table) {
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if (freq > div_table[0].freq)
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freq = div_table[0].freq;
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for (val = 0; div_table[val + 1].freq != 0; val++) {
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if (freq > div_table[val + 1].freq)
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break;
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}
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*postdiv = 1 << val;
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} else {
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for (val = 0; val < 5; val++) {
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*postdiv = 1 << val;
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if ((u64)freq * *postdiv >= fmin)
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break;
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}
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}
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/* _pcw = freq * postdiv / fin * 2^pcwfbits */
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ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
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_pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
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do_div(_pcw, fin);
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*pcw = (u32)_pcw;
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}
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static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
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u32 pcw = 0;
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u32 postdiv;
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mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
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mtk_pll_set_rate_regs(pll, pcw, postdiv);
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return 0;
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}
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static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
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u32 postdiv;
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u32 pcw;
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postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
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postdiv = 1 << postdiv;
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pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
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pcw &= GENMASK(pll->data->pcwbits - 1, 0);
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return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
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}
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static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
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u32 pcw = 0;
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int postdiv;
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mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
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return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
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}
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static int mtk_pll_prepare(struct clk_hw *hw)
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{
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struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
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u32 r;
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r = readl(pll->pwr_addr) | CON0_PWR_ON;
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writel(r, pll->pwr_addr);
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udelay(1);
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r = readl(pll->pwr_addr) & ~CON0_ISO_EN;
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writel(r, pll->pwr_addr);
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udelay(1);
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r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);
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writel(r, pll->en_addr);
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if (pll->data->en_mask) {
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r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
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writel(r, pll->base_addr + REG_CON0);
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}
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__mtk_pll_tuner_enable(pll);
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udelay(20);
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if (pll->data->flags & HAVE_RST_BAR) {
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r = readl(pll->base_addr + REG_CON0);
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r |= pll->data->rst_bar_mask;
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writel(r, pll->base_addr + REG_CON0);
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}
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return 0;
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}
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static void mtk_pll_unprepare(struct clk_hw *hw)
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{
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struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
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u32 r;
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if (pll->data->flags & HAVE_RST_BAR) {
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r = readl(pll->base_addr + REG_CON0);
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r &= ~pll->data->rst_bar_mask;
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writel(r, pll->base_addr + REG_CON0);
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}
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__mtk_pll_tuner_disable(pll);
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if (pll->data->en_mask) {
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r = readl(pll->base_addr + REG_CON0) & ~pll->data->en_mask;
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writel(r, pll->base_addr + REG_CON0);
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}
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r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit);
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writel(r, pll->en_addr);
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r = readl(pll->pwr_addr) | CON0_ISO_EN;
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writel(r, pll->pwr_addr);
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r = readl(pll->pwr_addr) & ~CON0_PWR_ON;
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writel(r, pll->pwr_addr);
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}
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static const struct clk_ops mtk_pll_ops = {
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.is_prepared = mtk_pll_is_prepared,
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.prepare = mtk_pll_prepare,
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.unprepare = mtk_pll_unprepare,
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.recalc_rate = mtk_pll_recalc_rate,
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.round_rate = mtk_pll_round_rate,
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.set_rate = mtk_pll_set_rate,
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};
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static struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
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void __iomem *base)
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{
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struct mtk_clk_pll *pll;
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struct clk_init_data init = {};
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int ret;
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const char *parent_name = "clk26m";
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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pll->base_addr = base + data->reg;
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pll->pwr_addr = base + data->pwr_reg;
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pll->pd_addr = base + data->pd_reg;
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pll->pcw_addr = base + data->pcw_reg;
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if (data->pcw_chg_reg)
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pll->pcw_chg_addr = base + data->pcw_chg_reg;
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else
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pll->pcw_chg_addr = pll->base_addr + REG_CON1;
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if (data->tuner_reg)
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pll->tuner_addr = base + data->tuner_reg;
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if (data->tuner_en_reg || data->tuner_en_bit)
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pll->tuner_en_addr = base + data->tuner_en_reg;
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if (data->en_reg)
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pll->en_addr = base + data->en_reg;
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else
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pll->en_addr = pll->base_addr + REG_CON0;
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pll->hw.init = &init;
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pll->data = data;
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init.name = data->name;
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init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
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init.ops = &mtk_pll_ops;
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if (data->parent_name)
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init.parent_names = &data->parent_name;
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else
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init.parent_names = &parent_name;
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init.num_parents = 1;
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ret = clk_hw_register(NULL, &pll->hw);
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if (ret) {
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kfree(pll);
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return ERR_PTR(ret);
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}
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return &pll->hw;
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}
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static void mtk_clk_unregister_pll(struct clk_hw *hw)
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{
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struct mtk_clk_pll *pll;
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if (!hw)
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return;
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pll = to_mtk_clk_pll(hw);
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clk_hw_unregister(hw);
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kfree(pll);
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}
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int mtk_clk_register_plls(struct device_node *node,
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const struct mtk_pll_data *plls, int num_plls,
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struct clk_hw_onecell_data *clk_data)
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{
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void __iomem *base;
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int i;
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struct clk_hw *hw;
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base = of_iomap(node, 0);
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if (!base) {
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pr_err("%s(): ioremap failed\n", __func__);
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return -EINVAL;
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}
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for (i = 0; i < num_plls; i++) {
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const struct mtk_pll_data *pll = &plls[i];
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if (!IS_ERR_OR_NULL(clk_data->hws[pll->id])) {
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pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
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node, pll->id);
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continue;
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}
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hw = mtk_clk_register_pll(pll, base);
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if (IS_ERR(hw)) {
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pr_err("Failed to register clk %s: %pe\n", pll->name,
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hw);
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goto err;
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}
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clk_data->hws[pll->id] = hw;
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}
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return 0;
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err:
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while (--i >= 0) {
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const struct mtk_pll_data *pll = &plls[i];
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mtk_clk_unregister_pll(clk_data->hws[pll->id]);
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clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
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}
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iounmap(base);
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return PTR_ERR(hw);
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}
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EXPORT_SYMBOL_GPL(mtk_clk_register_plls);
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static __iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
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const struct mtk_pll_data *data)
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{
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struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
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return pll->base_addr - data->reg;
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}
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void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
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struct clk_hw_onecell_data *clk_data)
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|
{
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__iomem void *base = NULL;
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int i;
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|
|
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if (!clk_data)
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return;
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|
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for (i = num_plls; i > 0; i--) {
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const struct mtk_pll_data *pll = &plls[i - 1];
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|
|
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if (IS_ERR_OR_NULL(clk_data->hws[pll->id]))
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|
continue;
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|
|
|
/*
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|
* This is quite ugly but unfortunately the clks don't have
|
|
* any device tied to them, so there's no place to store the
|
|
* pointer to the I/O region base address. We have to fetch
|
|
* it from one of the registered clks.
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|
*/
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base = mtk_clk_pll_get_base(clk_data->hws[pll->id], pll);
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|
|
|
mtk_clk_unregister_pll(clk_data->hws[pll->id]);
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|
clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
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|
}
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|
|
|
iounmap(base);
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|
}
|
|
EXPORT_SYMBOL_GPL(mtk_clk_unregister_plls);
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|
|
|
MODULE_LICENSE("GPL");
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