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![Taniya Das](/assets/img/avatar_default.png)
On SC7180 we observe black screens because the gdsc is being enabled/disabled very rapidly and the GDSC FSM state does not work as expected. This is due to the fact that the GDSC reset value is being updated from SW. The recommended transition delay for mdss core gdsc updated for SC7180/SC7280/SM8250. Fixes:dd3d066221
("clk: qcom: Add display clock controller driver for SC7180") Fixes:1a00c962f9
("clk: qcom: Add display clock controller driver for SC7280") Fixes:80a18f4a85
("clk: qcom: Add display clock controller driver for SM8150 and SM8250") Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/20220223185606.3941-2-tdas@codeaurora.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> [sboyd@kernel.org: lowercase hex] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
911 lines
24 KiB
C
911 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021-2022, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap-divider.h"
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#include "common.h"
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#include "gdsc.h"
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enum {
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P_BI_TCXO,
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P_DISP_CC_PLL0_OUT_EVEN,
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P_DISP_CC_PLL0_OUT_MAIN,
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P_DP_PHY_PLL_LINK_CLK,
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P_DP_PHY_PLL_VCO_DIV_CLK,
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P_DSI0_PHY_PLL_OUT_BYTECLK,
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P_DSI0_PHY_PLL_OUT_DSICLK,
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P_EDP_PHY_PLL_LINK_CLK,
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P_EDP_PHY_PLL_VCO_DIV_CLK,
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P_GCC_DISP_GPLL0_CLK,
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};
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static const struct pll_vco lucid_vco[] = {
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{ 249600000, 2000000000, 0 },
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};
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/* 1520MHz Configuration*/
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static const struct alpha_pll_config disp_cc_pll0_config = {
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.l = 0x4F,
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.alpha = 0x2AAA,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002261,
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.config_ctl_hi1_val = 0x329A299C,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00000805,
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.user_ctl_hi1_val = 0x00000000,
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};
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static struct clk_alpha_pll disp_cc_pll0 = {
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.offset = 0x0,
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.vco_table = lucid_vco,
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.num_vco = ARRAY_SIZE(lucid_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_pll0",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_ops,
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},
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},
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};
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static const struct parent_map disp_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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};
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static const struct clk_parent_data disp_cc_parent_data_0[] = {
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{ .fw_name = "bi_tcxo" },
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};
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static const struct parent_map disp_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_DP_PHY_PLL_LINK_CLK, 1 },
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{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
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};
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static const struct clk_parent_data disp_cc_parent_data_1[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "dp_phy_pll_link_clk" },
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{ .fw_name = "dp_phy_pll_vco_div_clk" },
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};
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static const struct parent_map disp_cc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
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};
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static const struct clk_parent_data disp_cc_parent_data_2[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "dsi0_phy_pll_out_byteclk" },
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};
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static const struct parent_map disp_cc_parent_map_3[] = {
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{ P_BI_TCXO, 0 },
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{ P_EDP_PHY_PLL_LINK_CLK, 1 },
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{ P_EDP_PHY_PLL_VCO_DIV_CLK, 2 },
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};
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static const struct clk_parent_data disp_cc_parent_data_3[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "edp_phy_pll_link_clk" },
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{ .fw_name = "edp_phy_pll_vco_div_clk" },
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};
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static const struct parent_map disp_cc_parent_map_4[] = {
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{ P_BI_TCXO, 0 },
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{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
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{ P_GCC_DISP_GPLL0_CLK, 4 },
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{ P_DISP_CC_PLL0_OUT_EVEN, 5 },
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};
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static const struct clk_parent_data disp_cc_parent_data_4[] = {
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{ .fw_name = "bi_tcxo" },
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{ .hw = &disp_cc_pll0.clkr.hw },
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{ .fw_name = "gcc_disp_gpll0_clk" },
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{ .hw = &disp_cc_pll0.clkr.hw },
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};
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static const struct parent_map disp_cc_parent_map_5[] = {
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{ P_BI_TCXO, 0 },
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{ P_GCC_DISP_GPLL0_CLK, 4 },
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};
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static const struct clk_parent_data disp_cc_parent_data_5[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "gcc_disp_gpll0_clk" },
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};
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static const struct parent_map disp_cc_parent_map_6[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
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};
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static const struct clk_parent_data disp_cc_parent_data_6[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0),
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F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
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.cmd_rcgr = 0x1170,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_5,
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.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_ahb_clk_src",
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.parent_data = disp_cc_parent_data_5,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
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.cmd_rcgr = 0x10d8,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_2,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte0_clk_src",
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.parent_data = disp_cc_parent_data_2,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
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.cmd_rcgr = 0x1158,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_0,
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.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_dp_aux_clk_src",
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.parent_data = disp_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
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.cmd_rcgr = 0x1128,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_1,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_dp_crypto_clk_src",
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.parent_data = disp_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
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.ops = &clk_byte2_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
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.cmd_rcgr = 0x110c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_1,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_dp_link_clk_src",
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.parent_data = disp_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
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.ops = &clk_byte2_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
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.cmd_rcgr = 0x1140,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_1,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_dp_pixel_clk_src",
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.parent_data = disp_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
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.ops = &clk_dp_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = {
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.cmd_rcgr = 0x11d0,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_0,
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.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_edp_aux_clk_src",
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.parent_data = disp_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = {
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.cmd_rcgr = 0x11a0,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_3,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_edp_link_clk_src",
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.parent_data = disp_cc_parent_data_3,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = {
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.cmd_rcgr = 0x1188,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_3,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_edp_pixel_clk_src",
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.parent_data = disp_cc_parent_data_3,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
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.ops = &clk_dp_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
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.cmd_rcgr = 0x10f4,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_2,
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.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_esc0_clk_src",
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.parent_data = disp_cc_parent_data_2,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
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.ops = &clk_rcg2_ops,
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},
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
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F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0),
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F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0),
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F(380000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
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F(506666667, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
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F(608000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
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.cmd_rcgr = 0x1090,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_4,
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.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_mdp_clk_src",
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.parent_data = disp_cc_parent_data_4,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
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.cmd_rcgr = 0x1078,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_6,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_pclk0_clk_src",
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.parent_data = disp_cc_parent_data_6,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_pixel_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
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.cmd_rcgr = 0x10a8,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_4,
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.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_rot_clk_src",
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.parent_data = disp_cc_parent_data_4,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
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.cmd_rcgr = 0x10c0,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_0,
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.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_vsync_clk_src",
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.parent_data = disp_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
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.reg = 0x10f0,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "disp_cc_mdss_byte0_div_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_byte0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_regmap_div_ops,
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},
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};
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static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
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.reg = 0x1124,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "disp_cc_mdss_dp_link_div_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_dp_link_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = {
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.reg = 0x11b8,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "disp_cc_mdss_edp_link_div_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_edp_link_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_branch disp_cc_mdss_ahb_clk = {
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.halt_reg = 0x1050,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1050,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_ahb_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_ahb_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_byte0_clk = {
|
|
.halt_reg = 0x1030,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1030,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_byte0_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_byte0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
|
|
.halt_reg = 0x1034,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1034,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_byte0_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dp_aux_clk = {
|
|
.halt_reg = 0x104c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x104c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_dp_aux_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dp_aux_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
|
|
.halt_reg = 0x1044,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1044,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_dp_crypto_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dp_link_clk = {
|
|
.halt_reg = 0x103c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x103c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_dp_link_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
|
|
.halt_reg = 0x1040,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1040,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_dp_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
|
|
.halt_reg = 0x1048,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1048,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_dp_pixel_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_edp_aux_clk = {
|
|
.halt_reg = 0x1060,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1060,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_edp_aux_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_edp_aux_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_edp_link_clk = {
|
|
.halt_reg = 0x1058,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1058,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_edp_link_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_edp_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_edp_link_intf_clk = {
|
|
.halt_reg = 0x105c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x105c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_edp_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_edp_link_div_clk_src.clkr.hw
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_edp_pixel_clk = {
|
|
.halt_reg = 0x1054,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1054,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_edp_pixel_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_edp_pixel_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_esc0_clk = {
|
|
.halt_reg = 0x1038,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1038,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_esc0_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_esc0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_mdp_clk = {
|
|
.halt_reg = 0x1014,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1014,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_mdp_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
|
|
.halt_reg = 0x1024,
|
|
.halt_check = BRANCH_HALT_VOTED,
|
|
.clkr = {
|
|
.enable_reg = 0x1024,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_mdp_lut_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
|
|
.halt_reg = 0x2004,
|
|
.halt_check = BRANCH_HALT_VOTED,
|
|
.clkr = {
|
|
.enable_reg = 0x2004,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_pclk0_clk = {
|
|
.halt_reg = 0x1010,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1010,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_pclk0_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_rot_clk = {
|
|
.halt_reg = 0x101c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x101c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_rot_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_rot_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
|
|
.halt_reg = 0x200c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x200c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_rscc_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
|
|
.halt_reg = 0x2008,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2008,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_rscc_vsync_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_mdss_vsync_clk = {
|
|
.halt_reg = 0x102c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x102c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_mdss_vsync_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch disp_cc_sleep_clk = {
|
|
.halt_reg = 0x5004,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x5004,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "disp_cc_sleep_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct gdsc disp_cc_mdss_core_gdsc = {
|
|
.gdscr = 0x1004,
|
|
.en_rest_wait_val = 0x2,
|
|
.en_few_wait_val = 0x2,
|
|
.clk_dis_wait_val = 0xf,
|
|
.pd = {
|
|
.name = "disp_cc_mdss_core_gdsc",
|
|
},
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
.flags = HW_CTRL | RETAIN_FF_ENABLE,
|
|
};
|
|
|
|
static struct clk_regmap *disp_cc_sc7280_clocks[] = {
|
|
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
|
|
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
|
|
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
|
|
[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
|
|
[DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
|
|
[DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
|
|
[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
|
|
[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
|
|
[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
|
|
&disp_cc_mdss_dp_link_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
|
|
[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
|
|
[DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr,
|
|
[DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr,
|
|
[DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr,
|
|
[DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr,
|
|
[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] =
|
|
&disp_cc_mdss_edp_link_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr,
|
|
[DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr,
|
|
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
|
|
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
|
|
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
|
|
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
|
|
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
|
|
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
|
|
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
|
|
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
|
|
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
|
|
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
|
|
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
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[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
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[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
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[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
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[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
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[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
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};
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|
|
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static struct gdsc *disp_cc_sc7280_gdscs[] = {
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[DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc,
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};
|
|
|
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static const struct regmap_config disp_cc_sc7280_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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|
.val_bits = 32,
|
|
.max_register = 0x10000,
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.fast_io = true,
|
|
};
|
|
|
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static const struct qcom_cc_desc disp_cc_sc7280_desc = {
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.config = &disp_cc_sc7280_regmap_config,
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.clks = disp_cc_sc7280_clocks,
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.num_clks = ARRAY_SIZE(disp_cc_sc7280_clocks),
|
|
.gdscs = disp_cc_sc7280_gdscs,
|
|
.num_gdscs = ARRAY_SIZE(disp_cc_sc7280_gdscs),
|
|
};
|
|
|
|
static const struct of_device_id disp_cc_sc7280_match_table[] = {
|
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{ .compatible = "qcom,sc7280-dispcc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, disp_cc_sc7280_match_table);
|
|
|
|
static int disp_cc_sc7280_probe(struct platform_device *pdev)
|
|
{
|
|
struct regmap *regmap;
|
|
|
|
regmap = qcom_cc_map(pdev, &disp_cc_sc7280_desc);
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
|
|
|
/*
|
|
* Keep the clocks always-ON
|
|
* DISP_CC_XO_CLK
|
|
*/
|
|
regmap_update_bits(regmap, 0x5008, BIT(0), BIT(0));
|
|
|
|
return qcom_cc_really_probe(pdev, &disp_cc_sc7280_desc, regmap);
|
|
}
|
|
|
|
static struct platform_driver disp_cc_sc7280_driver = {
|
|
.probe = disp_cc_sc7280_probe,
|
|
.driver = {
|
|
.name = "disp_cc-sc7280",
|
|
.of_match_table = disp_cc_sc7280_match_table,
|
|
},
|
|
};
|
|
|
|
static int __init disp_cc_sc7280_init(void)
|
|
{
|
|
return platform_driver_register(&disp_cc_sc7280_driver);
|
|
}
|
|
subsys_initcall(disp_cc_sc7280_init);
|
|
|
|
static void __exit disp_cc_sc7280_exit(void)
|
|
{
|
|
platform_driver_unregister(&disp_cc_sc7280_driver);
|
|
}
|
|
module_exit(disp_cc_sc7280_exit);
|
|
|
|
MODULE_DESCRIPTION("QTI DISP_CC sc7280 Driver");
|
|
MODULE_LICENSE("GPL v2");
|