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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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![Linus Torvalds](/assets/img/avatar_default.png)
clk_set_rate_range() works so that the frequency is re-evaulated each time the rate is changed. Previously we wouldn't let clk providers see a rate that was different if it was still within the range, which could be bad for power if the clk could run slower when a range expands. Now the clk provider can decide to do something differently when the constraints change. This broke Nvidia's clk driver so we had to wait for the fix for that to bake a little more in -next. The rate range patch series also introduced a kunit suite for the clk framework that we're going to extend in the next release. It already made it easy to find corner cases in the rate range patches so I'm excited to see it cover more clk code and increase our confidence in core framework patches in the future. I also added a kunit test for the basic clk gate code and that work will continue to cover more basic clk types: muxes, dividers, etc. Beyond the core code we have the usual set of clk driver updates and additions. Qualcomm again dominates the diffstat here with lots more SoCs being supported and i.MX follows afer that with a similar number of SoCs gaining clk drivers. Beyond those large additions there's drivers being modernized to use clk_parent_data so we can move away from global string names for all the clks in an SoC. Finally there's lots of little fixes all over the clk drivers for typos, warnings, and missing clks that aren't critical and get batched up waiting for the next merge window to open. Nothing super big stands out in the driver pile. Full details are below. Core: - Make clk_set_rate_range() re-evaluate the limits each time - Introduce various clk_set_rate_range() tests - Add clk_drop_range() to drop a previously set range New Drivers: - i.MXRT1050 clock driver and bindings - i.MX8DXL clock driver and bindings - i.MX93 clock driver and bindings - NCO blocks on Apple SoCs - Audio clks on StarFive JH7100 RISC-V SoC - Add support for the new Renesas RZ/V2L SoC - Qualcomm SDX65 A7 PLL - Qualcomm SM6350 GPU clks - Qualcomm SM6125, SM6350, QCS2290 display clks - Qualcomm MSM8226 multimedia clks Updates: - Kunit tests for clk-gate implementation - Terminate arrays with sentinels and make that clearer - Cleanup SPDX tags - Fix typos in comments - Mark mux table as const in clk-mux - Make the all_lists array const - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add support for dynamic mode - Clock configuration on Microchip PolarFire SoCs - Free allocations on probe error in Mediatek clk driver - Modernize Mediatek clk driver by consolidating code - Add watchdog (WDT), I2C, and pin function controller (PFC) clocks on Renesas R-Car S4-8 - Improve the clocks for the Rockchip rk3568 display outputs (parenting, pll-rates) - Use of_device_get_match_data() instead of open-coding on Rockchip rk3568 - Reintroduce the expected fractional-divider behaviour that disappeared with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - Remove SYS PLL 1/2 clock gates for i.MX8M* - Remove AUDIO MCLK ROOT from i.MX7D - Add fracn gppll clock type used by i.MX93 - Add new composite clock for i.MX93 - Add missing media mipi phy ref clock for i.MX8MP - Fix off by one in imx_lpcg_parse_clks_from_dt() - Rework for the imx pll14xx - sama7g5: One low priority fix for GCLK of PDMC - Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8 - Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3 - Add CAN-FD clocks on Renesas R-Car V3U - Qualcomm SC8280XP RPMCC - Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs - Rework Qualcomm GCC bindings and convert SDM845 camera bindig to YAML - Convert various Qualcomm drivers to use clk_parent_data - Remove test clocks from various Qualcomm drivers - Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS - Qualcomm SM8150 EMAC, PCIe, UFS GDSCs - Better pixel clk frequency support on Qualcomm RCG2 clks -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmJDd+gRHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSVB4A//QWPv7tssTuHvVDOPz2q9rJFbjG6/fsuY d8i30y4uTSCWO2eErVUNKxRmrR5/DFJZ20cqv5aTXbiUk5BrmCiD0hyb8RZIU4jD Kw+1pEvnbBWR6s5TK0spMS9Nz9Uq8DBwoeczHAVQrRZu0I8AkOvWlVH7GncejYOP KJJSiuByXHRLxudrLWTwwkz3xoDTZBeBcqNbBnatgXnPgSzBh0Uz+0q8r9V9Hugw +TwXoTVt+XDrX2ihPzZlfm9xoOTOP6GoP+FYCo8gCfW4N0VjUDr3+D95rJoI2gp/ O9UyAx1+tMLlkVxuHcX1npHDPX6Nrqan68DBV4LQRdhSO3dfVD95AE16GzMrD+2t nuIzT+rst42UUzipCK/8pHLd/YCcPmIsH4C25ZnaF/I59kI/seF3zbekMTY7hS8D q9sTZYj1X32aHGTtN6QK6QJIscGHYfnSG3M8VLOnhmWDKmW+6AWJ2MVZdcCqDgnS AXnx1p7gwd/lHV8P+e1YoiUyh5a3tJ2CFFdQCu0tPwL0xLehHyfjKqtjYZjL2+hl 6pF8KxEy6BiMEZWqXmIUJK6xWFO9VpQ2uPxtV8pCTIAXmOOPenWhH7lkeTtIDRc0 hzJURj9HEcpEDakC4/16yfr+YnEn/vjhhZ8a4Vymsnl2IsI71C17vDmRer875Bp/ KPMBn6I1naQ= =fP8L -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "There's one large change in the core clk framework here. We change how clk_set_rate_range() works so that the frequency is re-evaulated each time the rate is changed. Previously we wouldn't let clk providers see a rate that was different if it was still within the range, which could be bad for power if the clk could run slower when a range expands. Now the clk provider can decide to do something differently when the constraints change. This broke Nvidia's clk driver so we had to wait for the fix for that to bake a little more in -next. The rate range patch series also introduced a kunit suite for the clk framework that we're going to extend in the next release. It already made it easy to find corner cases in the rate range patches so I'm excited to see it cover more clk code and increase our confidence in core framework patches in the future. I also added a kunit test for the basic clk gate code and that work will continue to cover more basic clk types: muxes, dividers, etc. Beyond the core code we have the usual set of clk driver updates and additions. Qualcomm again dominates the diffstat here with lots more SoCs being supported and i.MX follows afer that with a similar number of SoCs gaining clk drivers. Beyond those large additions there's drivers being modernized to use clk_parent_data so we can move away from global string names for all the clks in an SoC. Finally there's lots of little fixes all over the clk drivers for typos, warnings, and missing clks that aren't critical and get batched up waiting for the next merge window to open. Nothing super big stands out in the driver pile. Full details are below. Core: - Make clk_set_rate_range() re-evaluate the limits each time - Introduce various clk_set_rate_range() tests - Add clk_drop_range() to drop a previously set range New Drivers: - i.MXRT1050 clock driver and bindings - i.MX8DXL clock driver and bindings - i.MX93 clock driver and bindings - NCO blocks on Apple SoCs - Audio clks on StarFive JH7100 RISC-V SoC - Add support for the new Renesas RZ/V2L SoC - Qualcomm SDX65 A7 PLL - Qualcomm SM6350 GPU clks - Qualcomm SM6125, SM6350, QCS2290 display clks - Qualcomm MSM8226 multimedia clks Updates: - Kunit tests for clk-gate implementation - Terminate arrays with sentinels and make that clearer - Cleanup SPDX tags - Fix typos in comments - Mark mux table as const in clk-mux - Make the all_lists array const - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add support for dynamic mode - Clock configuration on Microchip PolarFire SoCs - Free allocations on probe error in Mediatek clk driver - Modernize Mediatek clk driver by consolidating code - Add watchdog (WDT), I2C, and pin function controller (PFC) clocks on Renesas R-Car S4-8 - Improve the clocks for the Rockchip rk3568 display outputs (parenting, pll-rates) - Use of_device_get_match_data() instead of open-coding on Rockchip rk3568 - Reintroduce the expected fractional-divider behaviour that disappeared with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - Remove SYS PLL 1/2 clock gates for i.MX8M* - Remove AUDIO MCLK ROOT from i.MX7D - Add fracn gppll clock type used by i.MX93 - Add new composite clock for i.MX93 - Add missing media mipi phy ref clock for i.MX8MP - Fix off by one in imx_lpcg_parse_clks_from_dt() - Rework for the imx pll14xx - sama7g5: One low priority fix for GCLK of PDMC - Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8 - Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3 - Add CAN-FD clocks on Renesas R-Car V3U - Qualcomm SC8280XP RPMCC - Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs - Rework Qualcomm GCC bindings and convert SDM845 camera bindig to YAML - Convert various Qualcomm drivers to use clk_parent_data - Remove test clocks from various Qualcomm drivers - Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS - Qualcomm SM8150 EMAC, PCIe, UFS GDSCs - Better pixel clk frequency support on Qualcomm RCG2 clks" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits) clk: zynq: Update the parameters to zynq_clk_register_periph_clk clk: zynq: trivial warning fix clk: Drop the rate range on clk_put() clk: test: Test clk_set_rate_range on orphan mux clk: Initialize orphan req_rate dt-bindings: clock: drop useless consumer example dt-bindings: clock: renesas: Make example 'clocks' parsable clk: qcom: gcc-msm8994: Fix gpll4 width dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml clk: rs9: Add Renesas 9-series PCIe clock generator driver clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index() clk: visconti: prevent array overflow in visconti_clk_register_gates() dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator clk: sifive: Move all stuff into SoCs header files from C files clk: sifive: Add SoCs prefix in each SoCs-dependent data riscv: dts: Change the macro name of prci in each device node dt-bindings: change the macro name of prci in header files and example clk: sifive: duplicate the macro definitions for the time being clk: qcom: sm6125-gcc: fix typos in comments clk: ti: clkctrl: fix typos in comments ...
2728 lines
72 KiB
C
2728 lines
72 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/ctype.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,gcc-msm8994.h>
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#include "common.h"
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#include "clk-regmap.h"
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#include "clk-alpha-pll.h"
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#include "clk-rcg.h"
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#include "clk-branch.h"
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#include "reset.h"
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#include "gdsc.h"
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enum {
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P_XO,
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P_GPLL0,
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P_GPLL4,
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};
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static struct clk_alpha_pll gpll0_early = {
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.offset = 0,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.enable_reg = 0x1480,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpll0_early",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "xo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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},
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},
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};
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static struct clk_alpha_pll_postdiv gpll0 = {
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.offset = 0,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll0",
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.parent_names = (const char *[]) { "gpll0_early" },
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.num_parents = 1,
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.ops = &clk_alpha_pll_postdiv_ops,
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},
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};
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static struct clk_alpha_pll gpll4_early = {
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.offset = 0x1dc0,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.enable_reg = 0x1480,
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.enable_mask = BIT(4),
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.hw.init = &(struct clk_init_data){
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.name = "gpll4_early",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "xo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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},
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},
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};
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static struct clk_alpha_pll_postdiv gpll4 = {
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.offset = 0x1dc0,
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpll4",
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.parent_names = (const char *[]) { "gpll4_early" },
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.num_parents = 1,
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.ops = &clk_alpha_pll_postdiv_ops,
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},
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};
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static const struct parent_map gcc_xo_gpll0_map[] = {
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{ P_XO, 0 },
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{ P_GPLL0, 1 },
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};
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static const struct clk_parent_data gcc_xo_gpll0[] = {
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{ .fw_name = "xo" },
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{ .hw = &gpll0.clkr.hw },
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};
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static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
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{ P_XO, 0 },
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{ P_GPLL0, 1 },
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{ P_GPLL4, 5 },
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};
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static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
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{ .fw_name = "xo" },
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{ .hw = &gpll0.clkr.hw },
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{ .hw = &gpll4.clkr.hw },
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};
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static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
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F(50000000, P_GPLL0, 12, 0, 0),
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F(100000000, P_GPLL0, 6, 0, 0),
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F(150000000, P_GPLL0, 4, 0, 0),
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F(171430000, P_GPLL0, 3.5, 0, 0),
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F(200000000, P_GPLL0, 3, 0, 0),
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F(240000000, P_GPLL0, 2.5, 0, 0),
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{ }
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};
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static struct clk_rcg2 ufs_axi_clk_src = {
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.cmd_rcgr = 0x1d68,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = gcc_xo_gpll0_map,
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.freq_tbl = ftbl_ufs_axi_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "ufs_axi_clk_src",
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.parent_data = gcc_xo_gpll0,
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.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct freq_tbl ftbl_usb30_master_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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F(125000000, P_GPLL0, 1, 5, 24),
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{ }
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};
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static struct clk_rcg2 usb30_master_clk_src = {
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.cmd_rcgr = 0x03d4,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = gcc_xo_gpll0_map,
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.freq_tbl = ftbl_usb30_master_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "usb30_master_clk_src",
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.parent_data = gcc_xo_gpll0,
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.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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F(50000000, P_GPLL0, 12, 0, 0),
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{ }
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};
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static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
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.cmd_rcgr = 0x0660,
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.hid_width = 5,
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.parent_map = gcc_xo_gpll0_map,
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.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_qup1_i2c_apps_clk_src",
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.parent_data = gcc_xo_gpll0,
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.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
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F(960000, P_XO, 10, 1, 2),
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F(4800000, P_XO, 4, 0, 0),
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F(9600000, P_XO, 2, 0, 0),
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F(15000000, P_GPLL0, 10, 1, 4),
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F(19200000, P_XO, 1, 0, 0),
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F(24000000, P_GPLL0, 12.5, 1, 2),
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F(25000000, P_GPLL0, 12, 1, 2),
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F(48000000, P_GPLL0, 12.5, 0, 0),
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F(50000000, P_GPLL0, 12, 0, 0),
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{ }
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};
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static struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = {
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F(960000, P_XO, 10, 1, 2),
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F(4800000, P_XO, 4, 0, 0),
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F(9600000, P_XO, 2, 0, 0),
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F(15000000, P_GPLL0, 10, 1, 4),
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F(19200000, P_XO, 1, 0, 0),
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F(25000000, P_GPLL0, 12, 1, 2),
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F(50000000, P_GPLL0, 12, 0, 0),
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{ }
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};
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static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
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.cmd_rcgr = 0x064c,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = gcc_xo_gpll0_map,
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.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_qup1_spi_apps_clk_src",
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.parent_data = gcc_xo_gpll0,
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.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
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.cmd_rcgr = 0x06e0,
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.hid_width = 5,
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.parent_map = gcc_xo_gpll0_map,
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.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_qup2_i2c_apps_clk_src",
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.parent_data = gcc_xo_gpll0,
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.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
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F(960000, P_XO, 10, 1, 2),
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F(4800000, P_XO, 4, 0, 0),
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F(9600000, P_XO, 2, 0, 0),
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F(15000000, P_GPLL0, 10, 1, 4),
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F(19200000, P_XO, 1, 0, 0),
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F(24000000, P_GPLL0, 12.5, 1, 2),
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F(25000000, P_GPLL0, 12, 1, 2),
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F(42860000, P_GPLL0, 14, 0, 0),
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F(46150000, P_GPLL0, 13, 0, 0),
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{ }
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};
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static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
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.cmd_rcgr = 0x06cc,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = gcc_xo_gpll0_map,
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.freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_qup2_spi_apps_clk_src",
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.parent_data = gcc_xo_gpll0,
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.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
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.cmd_rcgr = 0x0760,
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.hid_width = 5,
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.parent_map = gcc_xo_gpll0_map,
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.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "blsp1_qup3_i2c_apps_clk_src",
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.parent_data = gcc_xo_gpll0,
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.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
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.ops = &clk_rcg2_ops,
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},
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};
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|
|
|
static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = {
|
|
F(960000, P_XO, 10, 1, 2),
|
|
F(4800000, P_XO, 4, 0, 0),
|
|
F(9600000, P_XO, 2, 0, 0),
|
|
F(15000000, P_GPLL0, 10, 1, 4),
|
|
F(19200000, P_XO, 1, 0, 0),
|
|
F(24000000, P_GPLL0, 12.5, 1, 2),
|
|
F(25000000, P_GPLL0, 12, 1, 2),
|
|
F(42860000, P_GPLL0, 14, 0, 0),
|
|
F(44440000, P_GPLL0, 13.5, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
|
|
.cmd_rcgr = 0x074c,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp1_qup3_spi_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
|
|
.cmd_rcgr = 0x07e0,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp1_qup4_i2c_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
|
|
.cmd_rcgr = 0x07cc,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp1_qup4_spi_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
|
|
.cmd_rcgr = 0x0860,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp1_qup5_i2c_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = {
|
|
F(960000, P_XO, 10, 1, 2),
|
|
F(4800000, P_XO, 4, 0, 0),
|
|
F(9600000, P_XO, 2, 0, 0),
|
|
F(15000000, P_GPLL0, 10, 1, 4),
|
|
F(19200000, P_XO, 1, 0, 0),
|
|
F(24000000, P_GPLL0, 12.5, 1, 2),
|
|
F(25000000, P_GPLL0, 12, 1, 2),
|
|
F(40000000, P_GPLL0, 15, 0, 0),
|
|
F(42860000, P_GPLL0, 14, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
|
|
.cmd_rcgr = 0x084c,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp1_qup5_spi_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
|
|
.cmd_rcgr = 0x08e0,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp1_qup6_i2c_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = {
|
|
F(960000, P_XO, 10, 1, 2),
|
|
F(4800000, P_XO, 4, 0, 0),
|
|
F(9600000, P_XO, 2, 0, 0),
|
|
F(15000000, P_GPLL0, 10, 1, 4),
|
|
F(19200000, P_XO, 1, 0, 0),
|
|
F(24000000, P_GPLL0, 12.5, 1, 2),
|
|
F(27906976, P_GPLL0, 1, 2, 43),
|
|
F(41380000, P_GPLL0, 15, 0, 0),
|
|
F(42860000, P_GPLL0, 14, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
|
|
.cmd_rcgr = 0x08cc,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp1_qup6_spi_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
|
|
F(3686400, P_GPLL0, 1, 96, 15625),
|
|
F(7372800, P_GPLL0, 1, 192, 15625),
|
|
F(14745600, P_GPLL0, 1, 384, 15625),
|
|
F(16000000, P_GPLL0, 5, 2, 15),
|
|
F(19200000, P_XO, 1, 0, 0),
|
|
F(24000000, P_GPLL0, 5, 1, 5),
|
|
F(32000000, P_GPLL0, 1, 4, 75),
|
|
F(40000000, P_GPLL0, 15, 0, 0),
|
|
F(46400000, P_GPLL0, 1, 29, 375),
|
|
F(48000000, P_GPLL0, 12.5, 0, 0),
|
|
F(51200000, P_GPLL0, 1, 32, 375),
|
|
F(56000000, P_GPLL0, 1, 7, 75),
|
|
F(58982400, P_GPLL0, 1, 1536, 15625),
|
|
F(60000000, P_GPLL0, 10, 0, 0),
|
|
F(63160000, P_GPLL0, 9.5, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
|
|
.cmd_rcgr = 0x068c,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp1_uart1_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
|
|
.cmd_rcgr = 0x070c,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp1_uart2_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
|
|
.cmd_rcgr = 0x078c,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp1_uart3_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
|
|
.cmd_rcgr = 0x080c,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp1_uart4_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
|
|
.cmd_rcgr = 0x088c,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp1_uart5_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
|
|
.cmd_rcgr = 0x090c,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp1_uart6_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
|
|
.cmd_rcgr = 0x09a0,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_qup1_i2c_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = {
|
|
F(960000, P_XO, 10, 1, 2),
|
|
F(4800000, P_XO, 4, 0, 0),
|
|
F(9600000, P_XO, 2, 0, 0),
|
|
F(15000000, P_GPLL0, 10, 1, 4),
|
|
F(19200000, P_XO, 1, 0, 0),
|
|
F(24000000, P_GPLL0, 12.5, 1, 2),
|
|
F(25000000, P_GPLL0, 12, 1, 2),
|
|
F(42860000, P_GPLL0, 14, 0, 0),
|
|
F(44440000, P_GPLL0, 13.5, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
|
|
.cmd_rcgr = 0x098c,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_qup1_spi_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
|
|
.cmd_rcgr = 0x0a20,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_qup2_i2c_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
|
|
.cmd_rcgr = 0x0a0c,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_qup2_spi_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = {
|
|
F(960000, P_XO, 10, 1, 2),
|
|
F(4800000, P_XO, 4, 0, 0),
|
|
F(9600000, P_XO, 2, 0, 0),
|
|
F(15000000, P_GPLL0, 10, 1, 4),
|
|
F(19200000, P_XO, 1, 0, 0),
|
|
F(24000000, P_GPLL0, 12.5, 1, 2),
|
|
F(25000000, P_GPLL0, 12, 1, 2),
|
|
F(42860000, P_GPLL0, 14, 0, 0),
|
|
F(48000000, P_GPLL0, 12.5, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
|
|
.cmd_rcgr = 0x0aa0,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_qup3_i2c_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
|
|
.cmd_rcgr = 0x0a8c,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_qup3_spi_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
|
|
.cmd_rcgr = 0x0b20,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_qup4_i2c_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
|
|
.cmd_rcgr = 0x0b0c,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_qup4_spi_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
|
|
.cmd_rcgr = 0x0ba0,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_qup5_i2c_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
|
|
.cmd_rcgr = 0x0b8c,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
/* BLSP1 QUP1 and BLSP2 QUP5 use the same freqs */
|
|
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_qup5_spi_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
|
|
.cmd_rcgr = 0x0c20,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_qup6_i2c_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = {
|
|
F(960000, P_XO, 10, 1, 2),
|
|
F(4800000, P_XO, 4, 0, 0),
|
|
F(9600000, P_XO, 2, 0, 0),
|
|
F(15000000, P_GPLL0, 10, 1, 4),
|
|
F(19200000, P_XO, 1, 0, 0),
|
|
F(24000000, P_GPLL0, 12.5, 1, 2),
|
|
F(25000000, P_GPLL0, 12, 1, 2),
|
|
F(44440000, P_GPLL0, 13.5, 0, 0),
|
|
F(48000000, P_GPLL0, 12.5, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
|
|
.cmd_rcgr = 0x0c0c,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_qup6_spi_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
|
|
.cmd_rcgr = 0x09cc,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_uart1_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
|
|
.cmd_rcgr = 0x0a4c,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_uart2_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
|
|
.cmd_rcgr = 0x0acc,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_uart3_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
|
|
.cmd_rcgr = 0x0b4c,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_uart4_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
|
|
.cmd_rcgr = 0x0bcc,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_uart5_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
|
|
.cmd_rcgr = 0x0c4c,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "blsp2_uart6_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_gp1_clk_src[] = {
|
|
F(19200000, P_XO, 1, 0, 0),
|
|
F(100000000, P_GPLL0, 6, 0, 0),
|
|
F(200000000, P_GPLL0, 3, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 gp1_clk_src = {
|
|
.cmd_rcgr = 0x1904,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_gp1_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "gp1_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_gp2_clk_src[] = {
|
|
F(19200000, P_XO, 1, 0, 0),
|
|
F(100000000, P_GPLL0, 6, 0, 0),
|
|
F(200000000, P_GPLL0, 3, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 gp2_clk_src = {
|
|
.cmd_rcgr = 0x1944,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_gp2_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "gp2_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_gp3_clk_src[] = {
|
|
F(19200000, P_XO, 1, 0, 0),
|
|
F(100000000, P_GPLL0, 6, 0, 0),
|
|
F(200000000, P_GPLL0, 3, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 gp3_clk_src = {
|
|
.cmd_rcgr = 0x1984,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_gp3_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "gp3_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
|
|
F(1011000, P_XO, 1, 1, 19),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 pcie_0_aux_clk_src = {
|
|
.cmd_rcgr = 0x1b00,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.freq_tbl = ftbl_pcie_0_aux_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "pcie_0_aux_clk_src",
|
|
.parent_data = &(const struct clk_parent_data){
|
|
.fw_name = "xo",
|
|
},
|
|
.num_parents = 1,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
|
|
F(125000000, P_XO, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 pcie_0_pipe_clk_src = {
|
|
.cmd_rcgr = 0x1adc,
|
|
.hid_width = 5,
|
|
.freq_tbl = ftbl_pcie_pipe_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "pcie_0_pipe_clk_src",
|
|
.parent_data = &(const struct clk_parent_data){
|
|
.fw_name = "xo",
|
|
},
|
|
.num_parents = 1,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
|
|
F(1011000, P_XO, 1, 1, 19),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 pcie_1_aux_clk_src = {
|
|
.cmd_rcgr = 0x1b80,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.freq_tbl = ftbl_pcie_1_aux_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "pcie_1_aux_clk_src",
|
|
.parent_data = &(const struct clk_parent_data){
|
|
.fw_name = "xo",
|
|
},
|
|
.num_parents = 1,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 pcie_1_pipe_clk_src = {
|
|
.cmd_rcgr = 0x1b5c,
|
|
.hid_width = 5,
|
|
.freq_tbl = ftbl_pcie_pipe_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "pcie_1_pipe_clk_src",
|
|
.parent_data = &(const struct clk_parent_data){
|
|
.fw_name = "xo",
|
|
},
|
|
.num_parents = 1,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_pdm2_clk_src[] = {
|
|
F(60000000, P_GPLL0, 10, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 pdm2_clk_src = {
|
|
.cmd_rcgr = 0x0cd0,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_pdm2_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "pdm2_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
|
|
F(144000, P_XO, 16, 3, 25),
|
|
F(400000, P_XO, 12, 1, 4),
|
|
F(20000000, P_GPLL0, 15, 1, 2),
|
|
F(25000000, P_GPLL0, 12, 1, 2),
|
|
F(50000000, P_GPLL0, 12, 0, 0),
|
|
F(100000000, P_GPLL0, 6, 0, 0),
|
|
F(192000000, P_GPLL4, 2, 0, 0),
|
|
F(384000000, P_GPLL4, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = {
|
|
F(144000, P_XO, 16, 3, 25),
|
|
F(400000, P_XO, 12, 1, 4),
|
|
F(20000000, P_GPLL0, 15, 1, 2),
|
|
F(25000000, P_GPLL0, 12, 1, 2),
|
|
F(50000000, P_GPLL0, 12, 0, 0),
|
|
F(100000000, P_GPLL0, 6, 0, 0),
|
|
F(172000000, P_GPLL4, 2, 0, 0),
|
|
F(344000000, P_GPLL4, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 sdcc1_apps_clk_src = {
|
|
.cmd_rcgr = 0x04d0,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_gpll4_map,
|
|
.freq_tbl = ftbl_sdcc1_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "sdcc1_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0_gpll4,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
|
|
.ops = &clk_rcg2_floor_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
|
|
F(144000, P_XO, 16, 3, 25),
|
|
F(400000, P_XO, 12, 1, 4),
|
|
F(20000000, P_GPLL0, 15, 1, 2),
|
|
F(25000000, P_GPLL0, 12, 1, 2),
|
|
F(50000000, P_GPLL0, 12, 0, 0),
|
|
F(100000000, P_GPLL0, 6, 0, 0),
|
|
F(200000000, P_GPLL0, 3, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 sdcc2_apps_clk_src = {
|
|
.cmd_rcgr = 0x0510,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_sdcc2_4_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "sdcc2_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_floor_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 sdcc3_apps_clk_src = {
|
|
.cmd_rcgr = 0x0550,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_sdcc2_4_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "sdcc3_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_floor_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 sdcc4_apps_clk_src = {
|
|
.cmd_rcgr = 0x0590,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_sdcc2_4_apps_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "sdcc4_apps_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_floor_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
|
|
F(105500, P_XO, 1, 1, 182),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 tsif_ref_clk_src = {
|
|
.cmd_rcgr = 0x0d90,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.freq_tbl = ftbl_tsif_ref_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "tsif_ref_clk_src",
|
|
.parent_data = &(const struct clk_parent_data){
|
|
.fw_name = "xo",
|
|
},
|
|
.num_parents = 1,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
|
|
F(19200000, P_XO, 1, 0, 0),
|
|
F(60000000, P_GPLL0, 10, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 usb30_mock_utmi_clk_src = {
|
|
.cmd_rcgr = 0x03e8,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "usb30_mock_utmi_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
|
|
F(1200000, P_XO, 16, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 usb3_phy_aux_clk_src = {
|
|
.cmd_rcgr = 0x1414,
|
|
.hid_width = 5,
|
|
.freq_tbl = ftbl_usb3_phy_aux_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "usb3_phy_aux_clk_src",
|
|
.parent_data = &(const struct clk_parent_data){
|
|
.fw_name = "xo",
|
|
},
|
|
.num_parents = 1,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
|
|
F(75000000, P_GPLL0, 8, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 usb_hs_system_clk_src = {
|
|
.cmd_rcgr = 0x0490,
|
|
.hid_width = 5,
|
|
.parent_map = gcc_xo_gpll0_map,
|
|
.freq_tbl = ftbl_usb_hs_system_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "usb_hs_system_clk_src",
|
|
.parent_data = gcc_xo_gpll0,
|
|
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_ahb_clk = {
|
|
.halt_reg = 0x05c4,
|
|
.halt_check = BRANCH_HALT_VOTED,
|
|
.clkr = {
|
|
.enable_reg = 0x1484,
|
|
.enable_mask = BIT(17),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
|
|
.halt_reg = 0x0648,
|
|
.clkr = {
|
|
.enable_reg = 0x0648,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_qup1_i2c_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
|
|
.halt_reg = 0x0644,
|
|
.clkr = {
|
|
.enable_reg = 0x0644,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_qup1_spi_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
|
|
.halt_reg = 0x06c8,
|
|
.clkr = {
|
|
.enable_reg = 0x06c8,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_qup2_i2c_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
|
|
.halt_reg = 0x06c4,
|
|
.clkr = {
|
|
.enable_reg = 0x06c4,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_qup2_spi_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
|
|
.halt_reg = 0x0748,
|
|
.clkr = {
|
|
.enable_reg = 0x0748,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_qup3_i2c_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
|
|
.halt_reg = 0x0744,
|
|
.clkr = {
|
|
.enable_reg = 0x0744,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_qup3_spi_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
|
|
.halt_reg = 0x07c8,
|
|
.clkr = {
|
|
.enable_reg = 0x07c8,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_qup4_i2c_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
|
|
.halt_reg = 0x07c4,
|
|
.clkr = {
|
|
.enable_reg = 0x07c4,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_qup4_spi_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
|
|
.halt_reg = 0x0848,
|
|
.clkr = {
|
|
.enable_reg = 0x0848,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_qup5_i2c_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
|
|
.halt_reg = 0x0844,
|
|
.clkr = {
|
|
.enable_reg = 0x0844,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_qup5_spi_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
|
|
.halt_reg = 0x08c8,
|
|
.clkr = {
|
|
.enable_reg = 0x08c8,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_qup6_i2c_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
|
|
.halt_reg = 0x08c4,
|
|
.clkr = {
|
|
.enable_reg = 0x08c4,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_qup6_spi_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
|
|
.halt_reg = 0x0684,
|
|
.clkr = {
|
|
.enable_reg = 0x0684,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_uart1_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
|
|
.halt_reg = 0x0704,
|
|
.clkr = {
|
|
.enable_reg = 0x0704,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_uart2_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_uart3_apps_clk = {
|
|
.halt_reg = 0x0784,
|
|
.clkr = {
|
|
.enable_reg = 0x0784,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_uart3_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_uart4_apps_clk = {
|
|
.halt_reg = 0x0804,
|
|
.clkr = {
|
|
.enable_reg = 0x0804,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_uart4_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_uart5_apps_clk = {
|
|
.halt_reg = 0x0884,
|
|
.clkr = {
|
|
.enable_reg = 0x0884,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_uart5_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp1_uart6_apps_clk = {
|
|
.halt_reg = 0x0904,
|
|
.clkr = {
|
|
.enable_reg = 0x0904,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp1_uart6_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_ahb_clk = {
|
|
.halt_reg = 0x0944,
|
|
.halt_check = BRANCH_HALT_VOTED,
|
|
.clkr = {
|
|
.enable_reg = 0x1484,
|
|
.enable_mask = BIT(15),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
|
|
.halt_reg = 0x0988,
|
|
.clkr = {
|
|
.enable_reg = 0x0988,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_qup1_i2c_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
|
|
.halt_reg = 0x0984,
|
|
.clkr = {
|
|
.enable_reg = 0x0984,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_qup1_spi_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
|
|
.halt_reg = 0x0a08,
|
|
.clkr = {
|
|
.enable_reg = 0x0a08,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_qup2_i2c_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
|
|
.halt_reg = 0x0a04,
|
|
.clkr = {
|
|
.enable_reg = 0x0a04,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_qup2_spi_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
|
|
.halt_reg = 0x0a88,
|
|
.clkr = {
|
|
.enable_reg = 0x0a88,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_qup3_i2c_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
|
|
.halt_reg = 0x0a84,
|
|
.clkr = {
|
|
.enable_reg = 0x0a84,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_qup3_spi_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
|
|
.halt_reg = 0x0b08,
|
|
.clkr = {
|
|
.enable_reg = 0x0b08,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_qup4_i2c_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
|
|
.halt_reg = 0x0b04,
|
|
.clkr = {
|
|
.enable_reg = 0x0b04,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_qup4_spi_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
|
|
.halt_reg = 0x0b88,
|
|
.clkr = {
|
|
.enable_reg = 0x0b88,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_qup5_i2c_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
|
|
.halt_reg = 0x0b84,
|
|
.clkr = {
|
|
.enable_reg = 0x0b84,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_qup5_spi_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
|
|
.halt_reg = 0x0c08,
|
|
.clkr = {
|
|
.enable_reg = 0x0c08,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_qup6_i2c_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
|
|
.halt_reg = 0x0c04,
|
|
.clkr = {
|
|
.enable_reg = 0x0c04,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_qup6_spi_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_uart1_apps_clk = {
|
|
.halt_reg = 0x09c4,
|
|
.clkr = {
|
|
.enable_reg = 0x09c4,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_uart1_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_uart2_apps_clk = {
|
|
.halt_reg = 0x0a44,
|
|
.clkr = {
|
|
.enable_reg = 0x0a44,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_uart2_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_uart3_apps_clk = {
|
|
.halt_reg = 0x0ac4,
|
|
.clkr = {
|
|
.enable_reg = 0x0ac4,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_uart3_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_uart4_apps_clk = {
|
|
.halt_reg = 0x0b44,
|
|
.clkr = {
|
|
.enable_reg = 0x0b44,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_uart4_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_uart5_apps_clk = {
|
|
.halt_reg = 0x0bc4,
|
|
.clkr = {
|
|
.enable_reg = 0x0bc4,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_uart5_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_blsp2_uart6_apps_clk = {
|
|
.halt_reg = 0x0c44,
|
|
.clkr = {
|
|
.enable_reg = 0x0c44,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_blsp2_uart6_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_gp1_clk = {
|
|
.halt_reg = 0x1900,
|
|
.clkr = {
|
|
.enable_reg = 0x1900,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_gp1_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_gp2_clk = {
|
|
.halt_reg = 0x1940,
|
|
.clkr = {
|
|
.enable_reg = 0x1940,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_gp2_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_gp3_clk = {
|
|
.halt_reg = 0x1980,
|
|
.clkr = {
|
|
.enable_reg = 0x1980,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_gp3_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_lpass_q6_axi_clk = {
|
|
.halt_reg = 0x0280,
|
|
.clkr = {
|
|
.enable_reg = 0x0280,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_lpass_q6_axi_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
|
|
.halt_reg = 0x0284,
|
|
.clkr = {
|
|
.enable_reg = 0x0284,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_mss_q6_bimc_axi_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_pcie_0_aux_clk = {
|
|
.halt_reg = 0x1ad4,
|
|
.clkr = {
|
|
.enable_reg = 0x1ad4,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_pcie_0_aux_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
|
|
.halt_reg = 0x1ad0,
|
|
.clkr = {
|
|
.enable_reg = 0x1ad0,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_pcie_0_cfg_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
|
|
.halt_reg = 0x1acc,
|
|
.clkr = {
|
|
.enable_reg = 0x1acc,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_pcie_0_mstr_axi_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_pcie_0_pipe_clk = {
|
|
.halt_reg = 0x1ad8,
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
.clkr = {
|
|
.enable_reg = 0x1ad8,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_pcie_0_pipe_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
|
|
.halt_reg = 0x1ac8,
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
.clkr = {
|
|
.enable_reg = 0x1ac8,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_pcie_0_slv_axi_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_pcie_1_aux_clk = {
|
|
.halt_reg = 0x1b54,
|
|
.clkr = {
|
|
.enable_reg = 0x1b54,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_pcie_1_aux_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
|
|
.halt_reg = 0x1b54,
|
|
.clkr = {
|
|
.enable_reg = 0x1b54,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_pcie_1_cfg_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
|
|
.halt_reg = 0x1b50,
|
|
.clkr = {
|
|
.enable_reg = 0x1b50,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_pcie_1_mstr_axi_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_pcie_1_pipe_clk = {
|
|
.halt_reg = 0x1b58,
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
.clkr = {
|
|
.enable_reg = 0x1b58,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_pcie_1_pipe_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
|
|
.halt_reg = 0x1b48,
|
|
.clkr = {
|
|
.enable_reg = 0x1b48,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_pcie_1_slv_axi_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_pdm2_clk = {
|
|
.halt_reg = 0x0ccc,
|
|
.clkr = {
|
|
.enable_reg = 0x0ccc,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_pdm2_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_pdm_ahb_clk = {
|
|
.halt_reg = 0x0cc4,
|
|
.clkr = {
|
|
.enable_reg = 0x0cc4,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_pdm_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_sdcc1_apps_clk = {
|
|
.halt_reg = 0x04c4,
|
|
.clkr = {
|
|
.enable_reg = 0x04c4,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_sdcc1_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_sdcc1_ahb_clk = {
|
|
.halt_reg = 0x04c8,
|
|
.clkr = {
|
|
.enable_reg = 0x04c8,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_sdcc1_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_sdcc2_ahb_clk = {
|
|
.halt_reg = 0x0508,
|
|
.clkr = {
|
|
.enable_reg = 0x0508,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_sdcc2_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_sdcc2_apps_clk = {
|
|
.halt_reg = 0x0504,
|
|
.clkr = {
|
|
.enable_reg = 0x0504,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_sdcc2_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_sdcc3_ahb_clk = {
|
|
.halt_reg = 0x0548,
|
|
.clkr = {
|
|
.enable_reg = 0x0548,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_sdcc3_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_sdcc3_apps_clk = {
|
|
.halt_reg = 0x0544,
|
|
.clkr = {
|
|
.enable_reg = 0x0544,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_sdcc3_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_sdcc4_ahb_clk = {
|
|
.halt_reg = 0x0588,
|
|
.clkr = {
|
|
.enable_reg = 0x0588,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_sdcc4_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_sdcc4_apps_clk = {
|
|
.halt_reg = 0x0584,
|
|
.clkr = {
|
|
.enable_reg = 0x0584,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_sdcc4_apps_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
|
|
.halt_reg = 0x1d7c,
|
|
.clkr = {
|
|
.enable_reg = 0x1d7c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_sys_noc_ufs_axi_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
|
|
.halt_reg = 0x03fc,
|
|
.clkr = {
|
|
.enable_reg = 0x03fc,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_sys_noc_usb3_axi_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_tsif_ahb_clk = {
|
|
.halt_reg = 0x0d84,
|
|
.clkr = {
|
|
.enable_reg = 0x0d84,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_tsif_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_tsif_ref_clk = {
|
|
.halt_reg = 0x0d88,
|
|
.clkr = {
|
|
.enable_reg = 0x0d88,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_tsif_ref_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_ufs_ahb_clk = {
|
|
.halt_reg = 0x1d4c,
|
|
.clkr = {
|
|
.enable_reg = 0x1d4c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_ufs_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_ufs_axi_clk = {
|
|
.halt_reg = 0x1d48,
|
|
.clkr = {
|
|
.enable_reg = 0x1d48,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_ufs_axi_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_ufs_rx_cfg_clk = {
|
|
.halt_reg = 0x1d54,
|
|
.clkr = {
|
|
.enable_reg = 0x1d54,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_ufs_rx_cfg_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
|
|
.halt_reg = 0x1d60,
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
.clkr = {
|
|
.enable_reg = 0x1d60,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_ufs_rx_symbol_0_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
|
|
.halt_reg = 0x1d64,
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
.clkr = {
|
|
.enable_reg = 0x1d64,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_ufs_rx_symbol_1_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_ufs_tx_cfg_clk = {
|
|
.halt_reg = 0x1d50,
|
|
.clkr = {
|
|
.enable_reg = 0x1d50,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_ufs_tx_cfg_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
|
|
.halt_reg = 0x1d58,
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
.clkr = {
|
|
.enable_reg = 0x1d58,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_ufs_tx_symbol_0_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
|
|
.halt_reg = 0x1d5c,
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
.clkr = {
|
|
.enable_reg = 0x1d5c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_ufs_tx_symbol_1_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_usb2_hs_phy_sleep_clk = {
|
|
.halt_reg = 0x04ac,
|
|
.clkr = {
|
|
.enable_reg = 0x04ac,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_usb2_hs_phy_sleep_clk",
|
|
.parent_data = &(const struct clk_parent_data){
|
|
.fw_name = "sleep",
|
|
.name = "sleep"
|
|
},
|
|
.num_parents = 1,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_usb30_master_clk = {
|
|
.halt_reg = 0x03c8,
|
|
.clkr = {
|
|
.enable_reg = 0x03c8,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_usb30_master_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_usb30_mock_utmi_clk = {
|
|
.halt_reg = 0x03d0,
|
|
.clkr = {
|
|
.enable_reg = 0x03d0,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_usb30_mock_utmi_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_usb30_sleep_clk = {
|
|
.halt_reg = 0x03cc,
|
|
.clkr = {
|
|
.enable_reg = 0x03cc,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_usb30_sleep_clk",
|
|
.parent_data = &(const struct clk_parent_data){
|
|
.fw_name = "sleep",
|
|
.name = "sleep"
|
|
},
|
|
.num_parents = 1,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_usb3_phy_aux_clk = {
|
|
.halt_reg = 0x1408,
|
|
.clkr = {
|
|
.enable_reg = 0x1408,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_usb3_phy_aux_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_usb3_phy_pipe_clk = {
|
|
.halt_reg = 0x140c,
|
|
.halt_check = BRANCH_HALT_SKIP,
|
|
.clkr = {
|
|
.enable_reg = 0x140c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_usb3_phy_pipe_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_usb_hs_ahb_clk = {
|
|
.halt_reg = 0x0488,
|
|
.clkr = {
|
|
.enable_reg = 0x0488,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_usb_hs_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_usb_hs_system_clk = {
|
|
.halt_reg = 0x0484,
|
|
.clkr = {
|
|
.enable_reg = 0x0484,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_usb_hs_system_clk",
|
|
.parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw },
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
|
|
.halt_reg = 0x1a84,
|
|
.clkr = {
|
|
.enable_reg = 0x1a84,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_usb_phy_cfg_ahb2phy_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gpll0_out_mmsscc = {
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
.clkr = {
|
|
.enable_reg = 0x1484,
|
|
.enable_mask = BIT(26),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gpll0_out_mmsscc",
|
|
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
|
|
.num_parents = 1,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gpll0_out_msscc = {
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
.clkr = {
|
|
.enable_reg = 0x1484,
|
|
.enable_mask = BIT(27),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gpll0_out_msscc",
|
|
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
|
|
.num_parents = 1,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch pcie_0_phy_ldo = {
|
|
.halt_reg = 0x1e00,
|
|
.halt_check = BRANCH_HALT_SKIP,
|
|
.clkr = {
|
|
.enable_reg = 0x1E00,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "pcie_0_phy_ldo",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch pcie_1_phy_ldo = {
|
|
.halt_reg = 0x1e04,
|
|
.halt_check = BRANCH_HALT_SKIP,
|
|
.clkr = {
|
|
.enable_reg = 0x1E04,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "pcie_1_phy_ldo",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch ufs_phy_ldo = {
|
|
.halt_reg = 0x1e0c,
|
|
.halt_check = BRANCH_HALT_SKIP,
|
|
.clkr = {
|
|
.enable_reg = 0x1E0C,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "ufs_phy_ldo",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch usb_ss_phy_ldo = {
|
|
.halt_reg = 0x1e08,
|
|
.halt_check = BRANCH_HALT_SKIP,
|
|
.clkr = {
|
|
.enable_reg = 0x1E08,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "usb_ss_phy_ldo",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_boot_rom_ahb_clk = {
|
|
.halt_reg = 0x0e04,
|
|
.halt_check = BRANCH_HALT_VOTED,
|
|
.hwcg_reg = 0x0e04,
|
|
.hwcg_bit = 1,
|
|
.clkr = {
|
|
.enable_reg = 0x1484,
|
|
.enable_mask = BIT(10),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_boot_rom_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gcc_prng_ahb_clk = {
|
|
.halt_reg = 0x0d04,
|
|
.halt_check = BRANCH_HALT_VOTED,
|
|
.clkr = {
|
|
.enable_reg = 0x1484,
|
|
.enable_mask = BIT(13),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gcc_prng_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct gdsc pcie_0_gdsc = {
|
|
.gdscr = 0x1ac4,
|
|
.pd = {
|
|
.name = "pcie_0",
|
|
},
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
};
|
|
|
|
static struct gdsc pcie_1_gdsc = {
|
|
.gdscr = 0x1b44,
|
|
.pd = {
|
|
.name = "pcie_1",
|
|
},
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
};
|
|
|
|
static struct gdsc usb30_gdsc = {
|
|
.gdscr = 0x3c4,
|
|
.pd = {
|
|
.name = "usb30",
|
|
},
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
};
|
|
|
|
static struct gdsc ufs_gdsc = {
|
|
.gdscr = 0x1d44,
|
|
.pd = {
|
|
.name = "ufs",
|
|
},
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
};
|
|
|
|
static struct clk_regmap *gcc_msm8994_clocks[] = {
|
|
[GPLL0_EARLY] = &gpll0_early.clkr,
|
|
[GPLL0] = &gpll0.clkr,
|
|
[GPLL4_EARLY] = &gpll4_early.clkr,
|
|
[GPLL4] = &gpll4.clkr,
|
|
[UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
|
|
[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
|
|
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
|
|
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
|
|
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
|
|
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
|
|
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
|
|
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
|
|
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
|
|
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
|
|
[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
|
|
[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
|
|
[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
|
|
[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
|
|
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
|
|
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
|
|
[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
|
|
[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
|
|
[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
|
|
[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
|
|
[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
|
|
[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
|
|
[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
|
|
[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
|
|
[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
|
|
[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
|
|
[BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
|
|
[BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
|
|
[BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
|
|
[BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
|
|
[BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
|
|
[BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
|
|
[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
|
|
[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
|
|
[BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
|
|
[BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
|
|
[BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
|
|
[BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
|
|
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
|
|
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
|
|
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
|
|
[PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
|
|
[PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
|
|
[PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
|
|
[PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
|
|
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
|
|
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
|
|
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
|
|
[SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
|
|
[SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
|
|
[TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
|
|
[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
|
|
[USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
|
|
[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
|
|
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
|
|
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
|
|
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
|
|
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
|
|
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
|
|
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
|
|
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
|
|
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
|
|
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
|
|
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
|
|
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
|
|
[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
|
|
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
|
|
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
|
|
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
|
|
[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
|
|
[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
|
|
[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
|
|
[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
|
|
[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
|
|
[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
|
|
[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
|
|
[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
|
|
[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
|
|
[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
|
|
[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
|
|
[GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
|
|
[GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
|
|
[GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
|
|
[GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
|
|
[GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
|
|
[GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
|
|
[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
|
|
[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
|
|
[GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
|
|
[GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
|
|
[GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
|
|
[GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
|
|
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
|
|
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
|
|
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
|
|
[GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
|
|
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
|
|
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
|
|
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
|
|
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
|
|
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
|
|
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
|
|
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
|
|
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
|
|
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
|
|
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
|
|
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
|
|
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
|
|
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
|
|
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
|
|
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
|
|
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
|
|
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
|
|
[GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
|
|
[GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
|
|
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
|
|
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
|
|
[GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
|
|
[GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
|
|
[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
|
|
[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
|
|
[GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
|
|
[GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
|
|
[GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
|
|
[GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
|
|
[GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
|
|
[GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
|
|
[GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
|
|
[GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
|
|
[GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr,
|
|
[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
|
|
[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
|
|
[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
|
|
[GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
|
|
[GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
|
|
[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
|
|
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
|
|
[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
|
|
[GPLL0_OUT_MMSSCC] = &gpll0_out_mmsscc.clkr,
|
|
[GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr,
|
|
[PCIE_0_PHY_LDO] = &pcie_0_phy_ldo.clkr,
|
|
[PCIE_1_PHY_LDO] = &pcie_1_phy_ldo.clkr,
|
|
[UFS_PHY_LDO] = &ufs_phy_ldo.clkr,
|
|
[USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr,
|
|
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
|
|
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
|
|
|
|
/*
|
|
* The following clocks should NOT be managed by this driver, but they once were
|
|
* mistakengly added. Now they are only here to indicate that they are not defined
|
|
* on purpose, even though the names will stay in the header file (for ABI sanity).
|
|
*/
|
|
[CONFIG_NOC_CLK_SRC] = NULL,
|
|
[PERIPH_NOC_CLK_SRC] = NULL,
|
|
[SYSTEM_NOC_CLK_SRC] = NULL,
|
|
};
|
|
|
|
static struct gdsc *gcc_msm8994_gdscs[] = {
|
|
/* This GDSC does not exist, but ABI has to remain intact */
|
|
[PCIE_GDSC] = NULL,
|
|
[PCIE_0_GDSC] = &pcie_0_gdsc,
|
|
[PCIE_1_GDSC] = &pcie_1_gdsc,
|
|
[USB30_GDSC] = &usb30_gdsc,
|
|
[UFS_GDSC] = &ufs_gdsc,
|
|
};
|
|
|
|
static const struct qcom_reset_map gcc_msm8994_resets[] = {
|
|
[USB3_PHY_RESET] = { 0x1400 },
|
|
[USB3PHY_PHY_RESET] = { 0x1404 },
|
|
[MSS_RESET] = { 0x1680 },
|
|
[PCIE_PHY_0_RESET] = { 0x1b18 },
|
|
[PCIE_PHY_1_RESET] = { 0x1b98 },
|
|
[QUSB2_PHY_RESET] = { 0x04b8 },
|
|
};
|
|
|
|
static const struct regmap_config gcc_msm8994_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = 0x2000,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static const struct qcom_cc_desc gcc_msm8994_desc = {
|
|
.config = &gcc_msm8994_regmap_config,
|
|
.clks = gcc_msm8994_clocks,
|
|
.num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
|
|
.resets = gcc_msm8994_resets,
|
|
.num_resets = ARRAY_SIZE(gcc_msm8994_resets),
|
|
.gdscs = gcc_msm8994_gdscs,
|
|
.num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs),
|
|
};
|
|
|
|
static const struct of_device_id gcc_msm8994_match_table[] = {
|
|
{ .compatible = "qcom,gcc-msm8992" },
|
|
{ .compatible = "qcom,gcc-msm8994" }, /* V2 and V2.1 */
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
|
|
|
|
static int gcc_msm8994_probe(struct platform_device *pdev)
|
|
{
|
|
if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-msm8992")) {
|
|
/* MSM8992 features less clocks and some have different freq tables */
|
|
gcc_msm8994_desc.clks[UFS_AXI_CLK_SRC] = NULL;
|
|
gcc_msm8994_desc.clks[GCC_LPASS_Q6_AXI_CLK] = NULL;
|
|
gcc_msm8994_desc.clks[UFS_PHY_LDO] = NULL;
|
|
gcc_msm8994_desc.clks[GCC_UFS_AHB_CLK] = NULL;
|
|
gcc_msm8994_desc.clks[GCC_UFS_AXI_CLK] = NULL;
|
|
gcc_msm8994_desc.clks[GCC_UFS_RX_CFG_CLK] = NULL;
|
|
gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_0_CLK] = NULL;
|
|
gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_1_CLK] = NULL;
|
|
gcc_msm8994_desc.clks[GCC_UFS_TX_CFG_CLK] = NULL;
|
|
gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_0_CLK] = NULL;
|
|
gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_1_CLK] = NULL;
|
|
|
|
sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_apps_clk_src_8992;
|
|
blsp1_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
|
|
blsp1_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
|
|
blsp1_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
|
|
blsp1_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
|
|
blsp1_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
|
|
blsp1_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
|
|
blsp2_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
|
|
blsp2_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
|
|
blsp2_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
|
|
blsp2_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
|
|
blsp2_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
|
|
blsp2_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
|
|
|
|
/*
|
|
* Some 8992 boards might *possibly* use
|
|
* PCIe1 clocks and controller, but it's not
|
|
* standard and they should be disabled otherwise.
|
|
*/
|
|
gcc_msm8994_desc.clks[PCIE_1_AUX_CLK_SRC] = NULL;
|
|
gcc_msm8994_desc.clks[PCIE_1_PIPE_CLK_SRC] = NULL;
|
|
gcc_msm8994_desc.clks[PCIE_1_PHY_LDO] = NULL;
|
|
gcc_msm8994_desc.clks[GCC_PCIE_1_AUX_CLK] = NULL;
|
|
gcc_msm8994_desc.clks[GCC_PCIE_1_CFG_AHB_CLK] = NULL;
|
|
gcc_msm8994_desc.clks[GCC_PCIE_1_MSTR_AXI_CLK] = NULL;
|
|
gcc_msm8994_desc.clks[GCC_PCIE_1_PIPE_CLK] = NULL;
|
|
gcc_msm8994_desc.clks[GCC_PCIE_1_SLV_AXI_CLK] = NULL;
|
|
gcc_msm8994_desc.clks[GCC_SYS_NOC_UFS_AXI_CLK] = NULL;
|
|
}
|
|
|
|
return qcom_cc_probe(pdev, &gcc_msm8994_desc);
|
|
}
|
|
|
|
static struct platform_driver gcc_msm8994_driver = {
|
|
.probe = gcc_msm8994_probe,
|
|
.driver = {
|
|
.name = "gcc-msm8994",
|
|
.of_match_table = gcc_msm8994_match_table,
|
|
},
|
|
};
|
|
|
|
static int __init gcc_msm8994_init(void)
|
|
{
|
|
return platform_driver_register(&gcc_msm8994_driver);
|
|
}
|
|
core_initcall(gcc_msm8994_init);
|
|
|
|
static void __exit gcc_msm8994_exit(void)
|
|
{
|
|
platform_driver_unregister(&gcc_msm8994_driver);
|
|
}
|
|
module_exit(gcc_msm8994_exit);
|
|
|
|
MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:gcc-msm8994");
|