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![Taniya Das](/assets/img/avatar_default.png)
GDSCs have multiple transition delays which are used for the GDSC FSM
states. Older targets/designs required these values to be updated from
gdsc code to certain default values for the FSM state to work as
expected. But on the newer targets/designs the values updated from the
GDSC driver can hamper the FSM state to not work as expected.
On SC7180 we observe black screens because the gdsc is being
enabled/disabled very rapidly and the GDSC FSM state does not work as
expected. This is due to the fact that the GDSC reset value is being
updated from SW.
Thus add support to update the transition delay from the clock
controller gdscs as required.
Fixes: 45dd0e5531
("clk: qcom: Add support for GDSCs)
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/20220223185606.3941-1-tdas@codeaurora.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
567 lines
13 KiB
C
567 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/export.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/ktime.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include "gdsc.h"
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#define PWR_ON_MASK BIT(31)
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#define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)
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#define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16)
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#define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12)
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#define SW_OVERRIDE_MASK BIT(2)
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#define HW_CONTROL_MASK BIT(1)
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#define SW_COLLAPSE_MASK BIT(0)
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#define GMEM_CLAMP_IO_MASK BIT(0)
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#define GMEM_RESET_MASK BIT(4)
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/* CFG_GDSCR */
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#define GDSC_POWER_UP_COMPLETE BIT(16)
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#define GDSC_POWER_DOWN_COMPLETE BIT(15)
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#define GDSC_RETAIN_FF_ENABLE BIT(11)
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#define CFG_GDSCR_OFFSET 0x4
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/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
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#define EN_REST_WAIT_VAL 0x2
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#define EN_FEW_WAIT_VAL 0x8
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#define CLK_DIS_WAIT_VAL 0x2
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/* Transition delay shifts */
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#define EN_REST_WAIT_SHIFT 20
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#define EN_FEW_WAIT_SHIFT 16
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#define CLK_DIS_WAIT_SHIFT 12
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#define RETAIN_MEM BIT(14)
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#define RETAIN_PERIPH BIT(13)
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#define TIMEOUT_US 500
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#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
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enum gdsc_status {
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GDSC_OFF,
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GDSC_ON
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};
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static int gdsc_pm_runtime_get(struct gdsc *sc)
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{
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if (!sc->dev)
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return 0;
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return pm_runtime_resume_and_get(sc->dev);
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}
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static int gdsc_pm_runtime_put(struct gdsc *sc)
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{
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if (!sc->dev)
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return 0;
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return pm_runtime_put_sync(sc->dev);
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}
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/* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
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static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
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{
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unsigned int reg;
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u32 val;
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int ret;
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if (sc->flags & POLL_CFG_GDSCR)
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reg = sc->gdscr + CFG_GDSCR_OFFSET;
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else if (sc->gds_hw_ctrl)
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reg = sc->gds_hw_ctrl;
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else
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reg = sc->gdscr;
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ret = regmap_read(sc->regmap, reg, &val);
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if (ret)
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return ret;
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if (sc->flags & POLL_CFG_GDSCR) {
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switch (status) {
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case GDSC_ON:
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return !!(val & GDSC_POWER_UP_COMPLETE);
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case GDSC_OFF:
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return !!(val & GDSC_POWER_DOWN_COMPLETE);
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}
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}
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switch (status) {
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case GDSC_ON:
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return !!(val & PWR_ON_MASK);
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case GDSC_OFF:
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return !(val & PWR_ON_MASK);
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}
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return -EINVAL;
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}
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static int gdsc_hwctrl(struct gdsc *sc, bool en)
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{
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u32 val = en ? HW_CONTROL_MASK : 0;
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return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
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}
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static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
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{
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ktime_t start;
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start = ktime_get();
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do {
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if (gdsc_check_status(sc, status))
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return 0;
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} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
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if (gdsc_check_status(sc, status))
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return 0;
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return -ETIMEDOUT;
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}
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static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
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{
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int ret;
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u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
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if (status == GDSC_ON && sc->rsupply) {
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ret = regulator_enable(sc->rsupply);
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if (ret < 0)
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return ret;
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}
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ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
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if (ret)
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return ret;
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/* If disabling votable gdscs, don't poll on status */
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if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
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/*
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* Add a short delay here to ensure that an enable
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* right after it was disabled does not put it in an
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* unknown state
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*/
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udelay(TIMEOUT_US);
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return 0;
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}
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if (sc->gds_hw_ctrl) {
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/*
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* The gds hw controller asserts/de-asserts the status bit soon
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* after it receives a power on/off request from a master.
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* The controller then takes around 8 xo cycles to start its
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* internal state machine and update the status bit. During
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* this time, the status bit does not reflect the true status
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* of the core.
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* Add a delay of 1 us between writing to the SW_COLLAPSE bit
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* and polling the status bit.
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*/
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udelay(1);
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}
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ret = gdsc_poll_status(sc, status);
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WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n");
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if (!ret && status == GDSC_OFF && sc->rsupply) {
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ret = regulator_disable(sc->rsupply);
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if (ret < 0)
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return ret;
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}
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return ret;
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}
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static inline int gdsc_deassert_reset(struct gdsc *sc)
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{
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int i;
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for (i = 0; i < sc->reset_count; i++)
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sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
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return 0;
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}
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static inline int gdsc_assert_reset(struct gdsc *sc)
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{
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int i;
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for (i = 0; i < sc->reset_count; i++)
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sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
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return 0;
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}
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static inline void gdsc_force_mem_on(struct gdsc *sc)
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{
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int i;
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u32 mask = RETAIN_MEM;
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if (!(sc->flags & NO_RET_PERIPH))
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mask |= RETAIN_PERIPH;
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for (i = 0; i < sc->cxc_count; i++)
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regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
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}
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static inline void gdsc_clear_mem_on(struct gdsc *sc)
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{
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int i;
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u32 mask = RETAIN_MEM;
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if (!(sc->flags & NO_RET_PERIPH))
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mask |= RETAIN_PERIPH;
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for (i = 0; i < sc->cxc_count; i++)
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regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
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}
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static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
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{
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regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
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GMEM_CLAMP_IO_MASK, 0);
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}
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static inline void gdsc_assert_clamp_io(struct gdsc *sc)
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{
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regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
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GMEM_CLAMP_IO_MASK, 1);
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}
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static inline void gdsc_assert_reset_aon(struct gdsc *sc)
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{
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regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
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GMEM_RESET_MASK, 1);
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udelay(1);
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regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
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GMEM_RESET_MASK, 0);
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}
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static void gdsc_retain_ff_on(struct gdsc *sc)
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{
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u32 mask = GDSC_RETAIN_FF_ENABLE;
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regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);
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}
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static int _gdsc_enable(struct gdsc *sc)
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{
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int ret;
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if (sc->pwrsts == PWRSTS_ON)
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return gdsc_deassert_reset(sc);
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if (sc->flags & SW_RESET) {
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gdsc_assert_reset(sc);
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udelay(1);
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gdsc_deassert_reset(sc);
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}
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if (sc->flags & CLAMP_IO) {
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if (sc->flags & AON_RESET)
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gdsc_assert_reset_aon(sc);
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gdsc_deassert_clamp_io(sc);
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}
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ret = gdsc_toggle_logic(sc, GDSC_ON);
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if (ret)
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return ret;
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if (sc->pwrsts & PWRSTS_OFF)
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gdsc_force_mem_on(sc);
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/*
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* If clocks to this power domain were already on, they will take an
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* additional 4 clock cycles to re-enable after the power domain is
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* enabled. Delay to account for this. A delay is also needed to ensure
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* clocks are not enabled within 400ns of enabling power to the
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* memories.
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*/
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udelay(1);
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/* Turn on HW trigger mode if supported */
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if (sc->flags & HW_CTRL) {
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ret = gdsc_hwctrl(sc, true);
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if (ret)
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return ret;
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/*
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* Wait for the GDSC to go through a power down and
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* up cycle. In case a firmware ends up polling status
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* bits for the gdsc, it might read an 'on' status before
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* the GDSC can finish the power cycle.
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* We wait 1us before returning to ensure the firmware
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* can't immediately poll the status bits.
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*/
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udelay(1);
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}
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if (sc->flags & RETAIN_FF_ENABLE)
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gdsc_retain_ff_on(sc);
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return 0;
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}
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static int gdsc_enable(struct generic_pm_domain *domain)
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{
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struct gdsc *sc = domain_to_gdsc(domain);
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int ret;
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ret = gdsc_pm_runtime_get(sc);
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if (ret)
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return ret;
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return _gdsc_enable(sc);
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}
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static int _gdsc_disable(struct gdsc *sc)
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{
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int ret;
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if (sc->pwrsts == PWRSTS_ON)
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return gdsc_assert_reset(sc);
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/* Turn off HW trigger mode if supported */
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if (sc->flags & HW_CTRL) {
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ret = gdsc_hwctrl(sc, false);
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if (ret < 0)
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return ret;
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/*
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* Wait for the GDSC to go through a power down and
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* up cycle. In case we end up polling status
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* bits for the gdsc before the power cycle is completed
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* it might read an 'on' status wrongly.
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*/
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udelay(1);
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ret = gdsc_poll_status(sc, GDSC_ON);
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if (ret)
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return ret;
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}
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if (sc->pwrsts & PWRSTS_OFF)
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gdsc_clear_mem_on(sc);
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ret = gdsc_toggle_logic(sc, GDSC_OFF);
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if (ret)
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return ret;
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if (sc->flags & CLAMP_IO)
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gdsc_assert_clamp_io(sc);
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return 0;
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}
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static int gdsc_disable(struct generic_pm_domain *domain)
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{
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struct gdsc *sc = domain_to_gdsc(domain);
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int ret;
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ret = _gdsc_disable(sc);
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gdsc_pm_runtime_put(sc);
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return ret;
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}
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static int gdsc_init(struct gdsc *sc)
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{
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u32 mask, val;
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int on, ret;
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/*
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* Disable HW trigger: collapse/restore occur based on registers writes.
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* Disable SW override: Use hardware state-machine for sequencing.
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* Configure wait time between states.
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*/
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mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
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EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
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if (!sc->en_rest_wait_val)
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sc->en_rest_wait_val = EN_REST_WAIT_VAL;
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if (!sc->en_few_wait_val)
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sc->en_few_wait_val = EN_FEW_WAIT_VAL;
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if (!sc->clk_dis_wait_val)
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sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL;
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val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT |
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sc->en_few_wait_val << EN_FEW_WAIT_SHIFT |
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sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT;
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ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
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if (ret)
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return ret;
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/* Force gdsc ON if only ON state is supported */
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if (sc->pwrsts == PWRSTS_ON) {
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ret = gdsc_toggle_logic(sc, GDSC_ON);
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if (ret)
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return ret;
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}
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on = gdsc_check_status(sc, GDSC_ON);
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if (on < 0)
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return on;
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if (on) {
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/* The regulator must be on, sync the kernel state */
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if (sc->rsupply) {
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ret = regulator_enable(sc->rsupply);
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if (ret < 0)
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return ret;
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}
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/*
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* Votable GDSCs can be ON due to Vote from other masters.
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* If a Votable GDSC is ON, make sure we have a Vote.
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*/
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if (sc->flags & VOTABLE) {
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ret = regmap_update_bits(sc->regmap, sc->gdscr,
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SW_COLLAPSE_MASK, val);
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if (ret)
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return ret;
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}
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/* Turn on HW trigger mode if supported */
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if (sc->flags & HW_CTRL) {
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ret = gdsc_hwctrl(sc, true);
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if (ret < 0)
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return ret;
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}
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/*
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* Make sure the retain bit is set if the GDSC is already on,
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* otherwise we end up turning off the GDSC and destroying all
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* the register contents that we thought we were saving.
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*/
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if (sc->flags & RETAIN_FF_ENABLE)
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gdsc_retain_ff_on(sc);
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} else if (sc->flags & ALWAYS_ON) {
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/* If ALWAYS_ON GDSCs are not ON, turn them ON */
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gdsc_enable(&sc->pd);
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on = true;
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}
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if (on || (sc->pwrsts & PWRSTS_RET))
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gdsc_force_mem_on(sc);
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else
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gdsc_clear_mem_on(sc);
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if (sc->flags & ALWAYS_ON)
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sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
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if (!sc->pd.power_off)
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sc->pd.power_off = gdsc_disable;
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if (!sc->pd.power_on)
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sc->pd.power_on = gdsc_enable;
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pm_genpd_init(&sc->pd, NULL, !on);
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return 0;
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}
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int gdsc_register(struct gdsc_desc *desc,
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struct reset_controller_dev *rcdev, struct regmap *regmap)
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{
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int i, ret;
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struct genpd_onecell_data *data;
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struct device *dev = desc->dev;
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struct gdsc **scs = desc->scs;
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size_t num = desc->num;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
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GFP_KERNEL);
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if (!data->domains)
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return -ENOMEM;
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for (i = 0; i < num; i++) {
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if (!scs[i] || !scs[i]->supply)
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continue;
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scs[i]->rsupply = devm_regulator_get(dev, scs[i]->supply);
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if (IS_ERR(scs[i]->rsupply))
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return PTR_ERR(scs[i]->rsupply);
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}
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data->num_domains = num;
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for (i = 0; i < num; i++) {
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if (!scs[i])
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continue;
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if (pm_runtime_enabled(dev))
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scs[i]->dev = dev;
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scs[i]->regmap = regmap;
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scs[i]->rcdev = rcdev;
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ret = gdsc_init(scs[i]);
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if (ret)
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return ret;
|
|
data->domains[i] = &scs[i]->pd;
|
|
}
|
|
|
|
/* Add subdomains */
|
|
for (i = 0; i < num; i++) {
|
|
if (!scs[i])
|
|
continue;
|
|
if (scs[i]->parent)
|
|
pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
|
|
else if (!IS_ERR_OR_NULL(dev->pm_domain))
|
|
pm_genpd_add_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd);
|
|
}
|
|
|
|
return of_genpd_add_provider_onecell(dev->of_node, data);
|
|
}
|
|
|
|
void gdsc_unregister(struct gdsc_desc *desc)
|
|
{
|
|
int i;
|
|
struct device *dev = desc->dev;
|
|
struct gdsc **scs = desc->scs;
|
|
size_t num = desc->num;
|
|
|
|
/* Remove subdomains */
|
|
for (i = 0; i < num; i++) {
|
|
if (!scs[i])
|
|
continue;
|
|
if (scs[i]->parent)
|
|
pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
|
|
else if (!IS_ERR_OR_NULL(dev->pm_domain))
|
|
pm_genpd_remove_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd);
|
|
}
|
|
of_genpd_del_provider(dev->of_node);
|
|
}
|
|
|
|
/*
|
|
* On SDM845+ the GPU GX domain is *almost* entirely controlled by the GMU
|
|
* running in the CX domain so the CPU doesn't need to know anything about the
|
|
* GX domain EXCEPT....
|
|
*
|
|
* Hardware constraints dictate that the GX be powered down before the CX. If
|
|
* the GMU crashes it could leave the GX on. In order to successfully bring back
|
|
* the device the CPU needs to disable the GX headswitch. There being no sane
|
|
* way to reach in and touch that register from deep inside the GPU driver we
|
|
* need to set up the infrastructure to be able to ensure that the GPU can
|
|
* ensure that the GX is off during this super special case. We do this by
|
|
* defining a GX gdsc with a dummy enable function and a "default" disable
|
|
* function.
|
|
*
|
|
* This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
|
|
* driver. During power up, nothing will happen from the CPU (and the GMU will
|
|
* power up normally but during power down this will ensure that the GX domain
|
|
* is *really* off - this gives us a semi standard way of doing what we need.
|
|
*/
|
|
int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain)
|
|
{
|
|
/* Do nothing but give genpd the impression that we were successful */
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable);
|