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![Vinod Koul](/assets/img/avatar_default.png)
Per Stephen, clk providers need to include clk-provider.h, so include in this driver as well Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211215113803.620032-5-vkoul@kernel.org
217 lines
5 KiB
C
217 lines
5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_runtime.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,lpass-sc7280.h>
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#include "clk-regmap.h"
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#include "clk-branch.h"
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#include "common.h"
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static struct clk_branch lpass_q6ss_ahbm_clk = {
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.halt_reg = 0x1c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "lpass_q6ss_ahbm_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch lpass_q6ss_ahbs_clk = {
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.halt_reg = 0x20,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x20,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "lpass_q6ss_ahbs_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
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.halt_reg = 0x0,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x0,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "lpass_top_cc_lpi_q6_axim_hs_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch lpass_qdsp6ss_core_clk = {
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.halt_reg = 0x20,
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/* CLK_OFF would not toggle until LPASS is out of reset */
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x20,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "lpass_qdsp6ss_core_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch lpass_qdsp6ss_xo_clk = {
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.halt_reg = 0x38,
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/* CLK_OFF would not toggle until LPASS is out of reset */
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x38,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "lpass_qdsp6ss_xo_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch lpass_qdsp6ss_sleep_clk = {
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.halt_reg = 0x3c,
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/* CLK_OFF would not toggle until LPASS is out of reset */
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x3c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "lpass_qdsp6ss_sleep_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct regmap_config lpass_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.fast_io = true,
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};
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static struct clk_regmap *lpass_cc_sc7280_clocks[] = {
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[LPASS_Q6SS_AHBM_CLK] = &lpass_q6ss_ahbm_clk.clkr,
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[LPASS_Q6SS_AHBS_CLK] = &lpass_q6ss_ahbs_clk.clkr,
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};
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static const struct qcom_cc_desc lpass_cc_sc7280_desc = {
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.config = &lpass_regmap_config,
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.clks = lpass_cc_sc7280_clocks,
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.num_clks = ARRAY_SIZE(lpass_cc_sc7280_clocks),
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};
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static struct clk_regmap *lpass_cc_top_sc7280_clocks[] = {
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[LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK] =
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&lpass_top_cc_lpi_q6_axim_hs_clk.clkr,
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};
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static const struct qcom_cc_desc lpass_cc_top_sc7280_desc = {
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.config = &lpass_regmap_config,
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.clks = lpass_cc_top_sc7280_clocks,
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.num_clks = ARRAY_SIZE(lpass_cc_top_sc7280_clocks),
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};
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static struct clk_regmap *lpass_qdsp6ss_sc7280_clocks[] = {
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[LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr,
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[LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr,
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[LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr,
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};
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static const struct qcom_cc_desc lpass_qdsp6ss_sc7280_desc = {
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.config = &lpass_regmap_config,
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.clks = lpass_qdsp6ss_sc7280_clocks,
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.num_clks = ARRAY_SIZE(lpass_qdsp6ss_sc7280_clocks),
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};
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static int lpass_cc_sc7280_probe(struct platform_device *pdev)
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{
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const struct qcom_cc_desc *desc;
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int ret;
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pm_runtime_enable(&pdev->dev);
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ret = pm_clk_create(&pdev->dev);
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if (ret)
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goto disable_pm_runtime;
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ret = pm_clk_add(&pdev->dev, "iface");
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to acquire iface clock\n");
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goto destroy_pm_clk;
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}
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lpass_regmap_config.name = "qdsp6ss";
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desc = &lpass_qdsp6ss_sc7280_desc;
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ret = qcom_cc_probe_by_index(pdev, 0, desc);
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if (ret)
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goto destroy_pm_clk;
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lpass_regmap_config.name = "top_cc";
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desc = &lpass_cc_top_sc7280_desc;
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ret = qcom_cc_probe_by_index(pdev, 1, desc);
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if (ret)
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goto destroy_pm_clk;
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lpass_regmap_config.name = "cc";
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desc = &lpass_cc_sc7280_desc;
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ret = qcom_cc_probe_by_index(pdev, 2, desc);
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if (ret)
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goto destroy_pm_clk;
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return 0;
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destroy_pm_clk:
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pm_clk_destroy(&pdev->dev);
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disable_pm_runtime:
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pm_runtime_disable(&pdev->dev);
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return ret;
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}
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static const struct of_device_id lpass_cc_sc7280_match_table[] = {
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{ .compatible = "qcom,sc7280-lpasscc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, lpass_cc_sc7280_match_table);
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static struct platform_driver lpass_cc_sc7280_driver = {
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.probe = lpass_cc_sc7280_probe,
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.driver = {
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.name = "sc7280-lpasscc",
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.of_match_table = lpass_cc_sc7280_match_table,
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},
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};
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static int __init lpass_cc_sc7280_init(void)
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{
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return platform_driver_register(&lpass_cc_sc7280_driver);
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}
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subsys_initcall(lpass_cc_sc7280_init);
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static void __exit lpass_cc_sc7280_exit(void)
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{
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platform_driver_unregister(&lpass_cc_sc7280_driver);
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}
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module_exit(lpass_cc_sc7280_exit);
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MODULE_DESCRIPTION("QTI LPASS_CC SC7280 Driver");
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MODULE_LICENSE("GPL v2");
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