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![Will McVicker](/assets/img/avatar_default.png)
Convert the remaining exynos clock drivers to use samsung_clk_register_cpu() or if possible use samsung_cmu_register_one(). With this we can now make exynos_register_cpu_clock() a static function so that future CPU clock registration changes will use the samsung common clock driver. The main benefit of this change is that it standardizes the CPU clock registration for the samsung clock drivers. Link: https://lore.kernel.org/r/20211015190515.3760577-1-willmcvicker@google.com Signed-off-by: Will McVicker <willmcvicker@google.com> Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> [snawrocki@kernel.org: Fixed build break in clk-exynos4.c, clk-exynos5250.c] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
489 lines
15 KiB
C
489 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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*
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* This file contains the utility function to register CPU clock for Samsung
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* Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a
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* group of CPUs. The CPU clock is typically derived from a hierarchy of clock
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* blocks which includes mux and divider blocks. There are a number of other
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* auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
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* clock for CPU domain. The rates of these auxiliary clocks are related to the
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* CPU clock rate and this relation is usually specified in the hardware manual
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* of the SoC or supplied after the SoC characterization.
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*
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* The below implementation of the CPU clock allows the rate changes of the CPU
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* clock and the corresponding rate changes of the auxillary clocks of the CPU
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* domain. The platform clock driver provides a clock register configuration
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* for each configurable rate which is then used to program the clock hardware
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* registers to acheive a fast co-oridinated rate change for all the CPU domain
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* clocks.
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*
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* On a rate change request for the CPU clock, the rate change is propagated
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* upto the PLL supplying the clock to the CPU domain clock blocks. While the
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* CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
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* alternate clock source. If required, the alternate clock source is divided
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* down in order to keep the output clock rate within the previous OPP limits.
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*/
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include "clk-cpu.h"
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#define E4210_SRC_CPU 0x0
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#define E4210_STAT_CPU 0x200
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#define E4210_DIV_CPU0 0x300
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#define E4210_DIV_CPU1 0x304
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#define E4210_DIV_STAT_CPU0 0x400
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#define E4210_DIV_STAT_CPU1 0x404
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#define E5433_MUX_SEL2 0x008
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#define E5433_MUX_STAT2 0x208
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#define E5433_DIV_CPU0 0x400
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#define E5433_DIV_CPU1 0x404
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#define E5433_DIV_STAT_CPU0 0x500
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#define E5433_DIV_STAT_CPU1 0x504
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#define E4210_DIV0_RATIO0_MASK 0x7
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#define E4210_DIV1_HPM_MASK (0x7 << 4)
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#define E4210_DIV1_COPY_MASK (0x7 << 0)
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#define E4210_MUX_HPM_MASK (1 << 20)
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#define E4210_DIV0_ATB_SHIFT 16
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#define E4210_DIV0_ATB_MASK (DIV_MASK << E4210_DIV0_ATB_SHIFT)
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#define MAX_DIV 8
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#define DIV_MASK 7
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#define DIV_MASK_ALL 0xffffffff
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#define MUX_MASK 7
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/*
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* Helper function to wait until divider(s) have stabilized after the divider
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* value has changed.
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*/
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static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(10);
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do {
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if (!(readl(div_reg) & mask))
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return;
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} while (time_before(jiffies, timeout));
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if (!(readl(div_reg) & mask))
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return;
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pr_err("%s: timeout in divider stablization\n", __func__);
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}
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/*
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* Helper function to wait until mux has stabilized after the mux selection
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* value was changed.
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*/
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static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
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unsigned long mux_value)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(10);
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do {
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if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
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return;
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} while (time_before(jiffies, timeout));
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if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
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return;
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pr_err("%s: re-parenting mux timed-out\n", __func__);
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}
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/* common round rate callback useable for all types of CPU clocks */
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static long exynos_cpuclk_round_rate(struct clk_hw *hw,
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unsigned long drate, unsigned long *prate)
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{
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struct clk_hw *parent = clk_hw_get_parent(hw);
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*prate = clk_hw_round_rate(parent, drate);
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return *prate;
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}
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/* common recalc rate callback useable for all types of CPU clocks */
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static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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/*
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* The CPU clock output (armclk) rate is the same as its parent
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* rate. Although there exist certain dividers inside the CPU
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* clock block that could be used to divide the parent clock,
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* the driver does not make use of them currently, except during
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* frequency transitions.
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*/
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return parent_rate;
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}
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static const struct clk_ops exynos_cpuclk_clk_ops = {
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.recalc_rate = exynos_cpuclk_recalc_rate,
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.round_rate = exynos_cpuclk_round_rate,
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};
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/*
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* Helper function to set the 'safe' dividers for the CPU clock. The parameters
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* div and mask contain the divider value and the register bit mask of the
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* dividers to be programmed.
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*/
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static void exynos_set_safe_div(void __iomem *base, unsigned long div,
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unsigned long mask)
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{
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unsigned long div0;
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div0 = readl(base + E4210_DIV_CPU0);
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div0 = (div0 & ~mask) | (div & mask);
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writel(div0, base + E4210_DIV_CPU0);
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wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, mask);
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}
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/* handler for pre-rate change notification from parent clock */
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static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
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struct exynos_cpuclk *cpuclk, void __iomem *base)
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{
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const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
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unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
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unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
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unsigned long div0, div1 = 0, mux_reg;
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unsigned long flags;
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/* find out the divider values to use for clock data */
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while ((cfg_data->prate * 1000) != ndata->new_rate) {
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if (cfg_data->prate == 0)
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return -EINVAL;
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cfg_data++;
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}
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spin_lock_irqsave(cpuclk->lock, flags);
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/*
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* For the selected PLL clock frequency, get the pre-defined divider
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* values. If the clock for sclk_hpm is not sourced from apll, then
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* the values for DIV_COPY and DIV_HPM dividers need not be set.
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*/
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div0 = cfg_data->div0;
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if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
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div1 = cfg_data->div1;
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if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK)
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div1 = readl(base + E4210_DIV_CPU1) &
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(E4210_DIV1_HPM_MASK | E4210_DIV1_COPY_MASK);
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}
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/*
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* If the old parent clock speed is less than the clock speed of
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* the alternate parent, then it should be ensured that at no point
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* the armclk speed is more than the old_prate until the dividers are
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* set. Also workaround the issue of the dividers being set to lower
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* values before the parent clock speed is set to new lower speed
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* (this can result in too high speed of armclk output clocks).
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*/
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if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
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unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
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alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
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WARN_ON(alt_div >= MAX_DIV);
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if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
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/*
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* In Exynos4210, ATB clock parent is also mout_core. So
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* ATB clock also needs to be mantained at safe speed.
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*/
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alt_div |= E4210_DIV0_ATB_MASK;
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alt_div_mask |= E4210_DIV0_ATB_MASK;
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}
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exynos_set_safe_div(base, alt_div, alt_div_mask);
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div0 |= alt_div;
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}
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/* select sclk_mpll as the alternate parent */
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mux_reg = readl(base + E4210_SRC_CPU);
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writel(mux_reg | (1 << 16), base + E4210_SRC_CPU);
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wait_until_mux_stable(base + E4210_STAT_CPU, 16, 2);
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/* alternate parent is active now. set the dividers */
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writel(div0, base + E4210_DIV_CPU0);
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wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, DIV_MASK_ALL);
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if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
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writel(div1, base + E4210_DIV_CPU1);
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wait_until_divider_stable(base + E4210_DIV_STAT_CPU1,
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DIV_MASK_ALL);
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}
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spin_unlock_irqrestore(cpuclk->lock, flags);
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return 0;
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}
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/* handler for post-rate change notification from parent clock */
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static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
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struct exynos_cpuclk *cpuclk, void __iomem *base)
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{
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const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
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unsigned long div = 0, div_mask = DIV_MASK;
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unsigned long mux_reg;
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unsigned long flags;
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/* find out the divider values to use for clock data */
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if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
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while ((cfg_data->prate * 1000) != ndata->new_rate) {
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if (cfg_data->prate == 0)
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return -EINVAL;
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cfg_data++;
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}
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}
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spin_lock_irqsave(cpuclk->lock, flags);
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/* select mout_apll as the alternate parent */
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mux_reg = readl(base + E4210_SRC_CPU);
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writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU);
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wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1);
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if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
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div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
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div_mask |= E4210_DIV0_ATB_MASK;
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}
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exynos_set_safe_div(base, div, div_mask);
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spin_unlock_irqrestore(cpuclk->lock, flags);
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return 0;
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}
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/*
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* Helper function to set the 'safe' dividers for the CPU clock. The parameters
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* div and mask contain the divider value and the register bit mask of the
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* dividers to be programmed.
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*/
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static void exynos5433_set_safe_div(void __iomem *base, unsigned long div,
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unsigned long mask)
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{
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unsigned long div0;
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div0 = readl(base + E5433_DIV_CPU0);
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div0 = (div0 & ~mask) | (div & mask);
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writel(div0, base + E5433_DIV_CPU0);
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wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, mask);
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}
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/* handler for pre-rate change notification from parent clock */
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static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
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struct exynos_cpuclk *cpuclk, void __iomem *base)
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{
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const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
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unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
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unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
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unsigned long div0, div1 = 0, mux_reg;
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unsigned long flags;
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/* find out the divider values to use for clock data */
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while ((cfg_data->prate * 1000) != ndata->new_rate) {
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if (cfg_data->prate == 0)
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return -EINVAL;
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cfg_data++;
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}
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spin_lock_irqsave(cpuclk->lock, flags);
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/*
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* For the selected PLL clock frequency, get the pre-defined divider
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* values.
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*/
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div0 = cfg_data->div0;
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div1 = cfg_data->div1;
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/*
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* If the old parent clock speed is less than the clock speed of
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* the alternate parent, then it should be ensured that at no point
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* the armclk speed is more than the old_prate until the dividers are
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* set. Also workaround the issue of the dividers being set to lower
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* values before the parent clock speed is set to new lower speed
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* (this can result in too high speed of armclk output clocks).
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*/
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if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
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unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
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alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
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WARN_ON(alt_div >= MAX_DIV);
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exynos5433_set_safe_div(base, alt_div, alt_div_mask);
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div0 |= alt_div;
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}
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/* select the alternate parent */
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mux_reg = readl(base + E5433_MUX_SEL2);
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writel(mux_reg | 1, base + E5433_MUX_SEL2);
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wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 2);
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/* alternate parent is active now. set the dividers */
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writel(div0, base + E5433_DIV_CPU0);
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wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, DIV_MASK_ALL);
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writel(div1, base + E5433_DIV_CPU1);
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wait_until_divider_stable(base + E5433_DIV_STAT_CPU1, DIV_MASK_ALL);
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spin_unlock_irqrestore(cpuclk->lock, flags);
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return 0;
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}
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/* handler for post-rate change notification from parent clock */
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static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
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struct exynos_cpuclk *cpuclk, void __iomem *base)
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{
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unsigned long div = 0, div_mask = DIV_MASK;
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unsigned long mux_reg;
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unsigned long flags;
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spin_lock_irqsave(cpuclk->lock, flags);
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/* select apll as the alternate parent */
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mux_reg = readl(base + E5433_MUX_SEL2);
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writel(mux_reg & ~1, base + E5433_MUX_SEL2);
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wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 1);
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exynos5433_set_safe_div(base, div, div_mask);
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spin_unlock_irqrestore(cpuclk->lock, flags);
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return 0;
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}
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/*
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* This notifier function is called for the pre-rate and post-rate change
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* notifications of the parent clock of cpuclk.
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*/
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static int exynos_cpuclk_notifier_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct clk_notifier_data *ndata = data;
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struct exynos_cpuclk *cpuclk;
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void __iomem *base;
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int err = 0;
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cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
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base = cpuclk->ctrl_base;
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if (event == PRE_RATE_CHANGE)
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err = exynos_cpuclk_pre_rate_change(ndata, cpuclk, base);
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else if (event == POST_RATE_CHANGE)
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err = exynos_cpuclk_post_rate_change(ndata, cpuclk, base);
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return notifier_from_errno(err);
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}
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/*
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* This notifier function is called for the pre-rate and post-rate change
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* notifications of the parent clock of cpuclk.
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*/
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static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct clk_notifier_data *ndata = data;
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struct exynos_cpuclk *cpuclk;
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void __iomem *base;
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int err = 0;
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cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
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base = cpuclk->ctrl_base;
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if (event == PRE_RATE_CHANGE)
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err = exynos5433_cpuclk_pre_rate_change(ndata, cpuclk, base);
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else if (event == POST_RATE_CHANGE)
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err = exynos5433_cpuclk_post_rate_change(ndata, cpuclk, base);
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return notifier_from_errno(err);
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}
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/* helper function to register a CPU clock */
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static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
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unsigned int lookup_id, const char *name,
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const struct clk_hw *parent, const struct clk_hw *alt_parent,
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unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg,
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unsigned long num_cfgs, unsigned long flags)
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{
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struct exynos_cpuclk *cpuclk;
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struct clk_init_data init;
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const char *parent_name;
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int ret = 0;
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if (IS_ERR(parent) || IS_ERR(alt_parent)) {
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pr_err("%s: invalid parent clock(s)\n", __func__);
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return -EINVAL;
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}
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cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
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if (!cpuclk)
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return -ENOMEM;
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parent_name = clk_hw_get_name(parent);
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init.name = name;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.ops = &exynos_cpuclk_clk_ops;
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cpuclk->alt_parent = alt_parent;
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cpuclk->hw.init = &init;
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cpuclk->ctrl_base = ctx->reg_base + offset;
|
|
cpuclk->lock = &ctx->lock;
|
|
cpuclk->flags = flags;
|
|
if (flags & CLK_CPU_HAS_E5433_REGS_LAYOUT)
|
|
cpuclk->clk_nb.notifier_call = exynos5433_cpuclk_notifier_cb;
|
|
else
|
|
cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
|
|
|
|
|
|
ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb);
|
|
if (ret) {
|
|
pr_err("%s: failed to register clock notifier for %s\n",
|
|
__func__, name);
|
|
goto free_cpuclk;
|
|
}
|
|
|
|
cpuclk->cfg = kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL);
|
|
if (!cpuclk->cfg) {
|
|
ret = -ENOMEM;
|
|
goto unregister_clk_nb;
|
|
}
|
|
|
|
ret = clk_hw_register(NULL, &cpuclk->hw);
|
|
if (ret) {
|
|
pr_err("%s: could not register cpuclk %s\n", __func__, name);
|
|
goto free_cpuclk_data;
|
|
}
|
|
|
|
samsung_clk_add_lookup(ctx, &cpuclk->hw, lookup_id);
|
|
return 0;
|
|
|
|
free_cpuclk_data:
|
|
kfree(cpuclk->cfg);
|
|
unregister_clk_nb:
|
|
clk_notifier_unregister(parent->clk, &cpuclk->clk_nb);
|
|
free_cpuclk:
|
|
kfree(cpuclk);
|
|
return ret;
|
|
}
|
|
|
|
void __init samsung_clk_register_cpu(struct samsung_clk_provider *ctx,
|
|
const struct samsung_cpu_clock *list, unsigned int nr_clk)
|
|
{
|
|
unsigned int idx;
|
|
unsigned int num_cfgs;
|
|
struct clk_hw **hws = ctx->clk_data.hws;
|
|
|
|
for (idx = 0; idx < nr_clk; idx++, list++) {
|
|
/* find count of configuration rates in cfg */
|
|
for (num_cfgs = 0; list->cfg[num_cfgs].prate != 0; )
|
|
num_cfgs++;
|
|
|
|
exynos_register_cpu_clock(ctx, list->id, list->name, hws[list->parent_id],
|
|
hws[list->alt_parent_id], list->offset, list->cfg, num_cfgs,
|
|
list->flags);
|
|
}
|
|
}
|