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ac48ea3b67
Convert the remaining exynos clock drivers to use samsung_clk_register_cpu() or if possible use samsung_cmu_register_one(). With this we can now make exynos_register_cpu_clock() a static function so that future CPU clock registration changes will use the samsung common clock driver. The main benefit of this change is that it standardizes the CPU clock registration for the samsung clock drivers. Link: https://lore.kernel.org/r/20211015190515.3760577-1-willmcvicker@google.com Signed-off-by: Will McVicker <willmcvicker@google.com> Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> [snawrocki@kernel.org: Fixed build break in clk-exynos4.c, clk-exynos5250.c] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
65 lines
2.2 KiB
C
65 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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*
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* Common Clock Framework support for all PLL's in Samsung platforms
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*/
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#ifndef __SAMSUNG_CLK_CPU_H
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#define __SAMSUNG_CLK_CPU_H
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#include "clk.h"
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/**
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* struct exynos_cpuclk_data: config data to setup cpu clocks.
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* @prate: frequency of the primary parent clock (in KHz).
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* @div0: value to be programmed in the div_cpu0 register.
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* @div1: value to be programmed in the div_cpu1 register.
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*
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* This structure holds the divider configuration data for dividers in the CPU
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* clock domain. The parent frequency at which these divider values are valid is
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* specified in @prate. The @prate is the frequency of the primary parent clock.
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* For CPU clock domains that do not have a DIV1 register, the @div1 member
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* value is not used.
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*/
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struct exynos_cpuclk_cfg_data {
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unsigned long prate;
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unsigned long div0;
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unsigned long div1;
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};
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/**
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* struct exynos_cpuclk: information about clock supplied to a CPU core.
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* @hw: handle between CCF and CPU clock.
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* @alt_parent: alternate parent clock to use when switching the speed
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* of the primary parent clock.
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* @ctrl_base: base address of the clock controller.
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* @lock: cpu clock domain register access lock.
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* @cfg: cpu clock rate configuration data.
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* @num_cfgs: number of array elements in @cfg array.
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* @clk_nb: clock notifier registered for changes in clock speed of the
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* primary parent clock.
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* @flags: configuration flags for the CPU clock.
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*
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* This structure holds information required for programming the CPU clock for
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* various clock speeds.
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*/
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struct exynos_cpuclk {
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struct clk_hw hw;
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const struct clk_hw *alt_parent;
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void __iomem *ctrl_base;
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spinlock_t *lock;
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const struct exynos_cpuclk_cfg_data *cfg;
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const unsigned long num_cfgs;
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struct notifier_block clk_nb;
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unsigned long flags;
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/* The CPU clock registers have DIV1 configuration register */
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#define CLK_CPU_HAS_DIV1 (1 << 0)
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/* When ALT parent is active, debug clocks need safe divider values */
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#define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1)
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/* The CPU clock registers have Exynos5433-compatible layout */
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#define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2)
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};
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#endif /* __SAMSUNG_CLK_CPU_H */
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