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![Tom Rix](/assets/img/avatar_default.png)
Replace tabs with spaces in SPDX tag Signed-off-by: Tom Rix <trix@redhat.com> Link: https://lore.kernel.org/r/20220217173453.3262672-1-trix@redhat.com Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
216 lines
5.1 KiB
C
216 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017, Intel Corporation
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*/
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#include <linux/slab.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include "stratix10-clk.h"
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#include "clk.h"
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#define CLK_MGR_FREE_SHIFT 16
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#define CLK_MGR_FREE_MASK 0x7
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#define SWCTRLBTCLKSEN_SHIFT 8
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#define to_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
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static unsigned long n5x_clk_peri_c_clk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
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unsigned long div;
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unsigned long shift = socfpgaclk->shift;
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u32 val;
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val = readl(socfpgaclk->hw.reg);
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val &= (0x1f << shift);
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div = (val >> shift) + 1;
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return parent_rate / div;
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}
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static unsigned long clk_peri_c_clk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
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unsigned long div = 1;
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u32 val;
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val = readl(socfpgaclk->hw.reg);
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val &= GENMASK(SWCTRLBTCLKSEN_SHIFT - 1, 0);
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parent_rate /= val;
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return parent_rate / div;
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}
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static unsigned long clk_peri_cnt_clk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
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unsigned long div = 1;
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if (socfpgaclk->fixed_div) {
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div = socfpgaclk->fixed_div;
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} else {
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if (socfpgaclk->hw.reg)
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div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
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}
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return parent_rate / div;
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}
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static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
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{
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struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
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u32 clk_src, mask;
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u8 parent = 0;
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/* handle the bypass first */
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if (socfpgaclk->bypass_reg) {
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mask = (0x1 << socfpgaclk->bypass_shift);
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parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
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socfpgaclk->bypass_shift);
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if (parent)
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return parent;
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}
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if (socfpgaclk->hw.reg) {
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clk_src = readl(socfpgaclk->hw.reg);
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parent = (clk_src >> CLK_MGR_FREE_SHIFT) &
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CLK_MGR_FREE_MASK;
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}
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return parent;
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}
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static const struct clk_ops n5x_peri_c_clk_ops = {
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.recalc_rate = n5x_clk_peri_c_clk_recalc_rate,
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.get_parent = clk_periclk_get_parent,
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};
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static const struct clk_ops peri_c_clk_ops = {
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.recalc_rate = clk_peri_c_clk_recalc_rate,
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.get_parent = clk_periclk_get_parent,
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};
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static const struct clk_ops peri_cnt_clk_ops = {
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.recalc_rate = clk_peri_cnt_clk_recalc_rate,
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.get_parent = clk_periclk_get_parent,
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};
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struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
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void __iomem *reg)
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{
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struct clk_hw *hw_clk;
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struct socfpga_periph_clk *periph_clk;
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struct clk_init_data init;
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const char *name = clks->name;
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const char *parent_name = clks->parent_name;
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int ret;
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periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
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if (WARN_ON(!periph_clk))
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return NULL;
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periph_clk->hw.reg = reg + clks->offset;
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init.name = name;
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init.ops = &peri_c_clk_ops;
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init.flags = clks->flags;
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init.num_parents = clks->num_parents;
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init.parent_names = parent_name ? &parent_name : NULL;
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if (init.parent_names == NULL)
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init.parent_data = clks->parent_data;
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periph_clk->hw.hw.init = &init;
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hw_clk = &periph_clk->hw.hw;
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ret = clk_hw_register(NULL, hw_clk);
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if (ret) {
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kfree(periph_clk);
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return ERR_PTR(ret);
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}
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return hw_clk;
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}
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struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks,
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void __iomem *regbase)
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{
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struct clk_hw *hw_clk;
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struct socfpga_periph_clk *periph_clk;
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struct clk_init_data init;
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const char *name = clks->name;
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const char *parent_name = clks->parent_name;
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int ret;
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periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
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if (WARN_ON(!periph_clk))
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return NULL;
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periph_clk->hw.reg = regbase + clks->offset;
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periph_clk->shift = clks->shift;
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init.name = name;
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init.ops = &n5x_peri_c_clk_ops;
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init.flags = clks->flags;
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init.num_parents = clks->num_parents;
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init.parent_names = parent_name ? &parent_name : NULL;
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periph_clk->hw.hw.init = &init;
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hw_clk = &periph_clk->hw.hw;
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ret = clk_hw_register(NULL, hw_clk);
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if (ret) {
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kfree(periph_clk);
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return ERR_PTR(ret);
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}
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return hw_clk;
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}
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struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
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void __iomem *regbase)
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{
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struct clk_hw *hw_clk;
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struct socfpga_periph_clk *periph_clk;
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struct clk_init_data init;
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const char *name = clks->name;
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const char *parent_name = clks->parent_name;
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int ret;
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periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
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if (WARN_ON(!periph_clk))
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return NULL;
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if (clks->offset)
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periph_clk->hw.reg = regbase + clks->offset;
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else
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periph_clk->hw.reg = NULL;
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if (clks->bypass_reg)
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periph_clk->bypass_reg = regbase + clks->bypass_reg;
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else
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periph_clk->bypass_reg = NULL;
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periph_clk->bypass_shift = clks->bypass_shift;
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periph_clk->fixed_div = clks->fixed_divider;
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init.name = name;
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init.ops = &peri_cnt_clk_ops;
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init.flags = clks->flags;
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init.num_parents = clks->num_parents;
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init.parent_names = parent_name ? &parent_name : NULL;
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if (init.parent_names == NULL)
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init.parent_data = clks->parent_data;
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periph_clk->hw.hw.init = &init;
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hw_clk = &periph_clk->hw.hw;
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ret = clk_hw_register(NULL, hw_clk);
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if (ret) {
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kfree(periph_clk);
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return ERR_PTR(ret);
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}
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return hw_clk;
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}
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