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![Alain Volmat](/assets/img/avatar_default.png)
In order to avoid relying on the old style description via the DT clock-output-names, add compatible data describing the flexgen outputs clocks for all STiH407/STiH410 and STiH418 SOCs. In order to ease transition between the two methods, this commit introduce the new compatible without removing the old method. Once DTs will be fixed, the method relying on DT clock-output-names will be removed from this driver as well as old compatibles. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210331201632.24530-3-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
748 lines
20 KiB
C
748 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* clk-flexgen.c
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*
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* Copyright (C) ST-Microelectronics SA 2013
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* Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/string.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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struct clkgen_clk_out {
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const char *name;
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unsigned long flags;
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};
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struct clkgen_data {
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unsigned long flags;
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bool mode;
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const struct clkgen_clk_out *outputs;
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const unsigned int outputs_nb;
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};
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struct flexgen {
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struct clk_hw hw;
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/* Crossbar */
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struct clk_mux mux;
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/* Pre-divisor's gate */
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struct clk_gate pgate;
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/* Pre-divisor */
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struct clk_divider pdiv;
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/* Final divisor's gate */
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struct clk_gate fgate;
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/* Final divisor */
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struct clk_divider fdiv;
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/* Asynchronous mode control */
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struct clk_gate sync;
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/* hw control flags */
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bool control_mode;
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};
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#define to_flexgen(_hw) container_of(_hw, struct flexgen, hw)
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#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
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static int flexgen_enable(struct clk_hw *hw)
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{
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struct flexgen *flexgen = to_flexgen(hw);
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struct clk_hw *pgate_hw = &flexgen->pgate.hw;
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struct clk_hw *fgate_hw = &flexgen->fgate.hw;
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__clk_hw_set_clk(pgate_hw, hw);
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__clk_hw_set_clk(fgate_hw, hw);
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clk_gate_ops.enable(pgate_hw);
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clk_gate_ops.enable(fgate_hw);
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pr_debug("%s: flexgen output enabled\n", clk_hw_get_name(hw));
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return 0;
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}
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static void flexgen_disable(struct clk_hw *hw)
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{
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struct flexgen *flexgen = to_flexgen(hw);
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struct clk_hw *fgate_hw = &flexgen->fgate.hw;
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/* disable only the final gate */
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__clk_hw_set_clk(fgate_hw, hw);
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clk_gate_ops.disable(fgate_hw);
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pr_debug("%s: flexgen output disabled\n", clk_hw_get_name(hw));
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}
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static int flexgen_is_enabled(struct clk_hw *hw)
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{
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struct flexgen *flexgen = to_flexgen(hw);
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struct clk_hw *fgate_hw = &flexgen->fgate.hw;
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__clk_hw_set_clk(fgate_hw, hw);
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if (!clk_gate_ops.is_enabled(fgate_hw))
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return 0;
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return 1;
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}
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static u8 flexgen_get_parent(struct clk_hw *hw)
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{
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struct flexgen *flexgen = to_flexgen(hw);
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struct clk_hw *mux_hw = &flexgen->mux.hw;
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__clk_hw_set_clk(mux_hw, hw);
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return clk_mux_ops.get_parent(mux_hw);
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}
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static int flexgen_set_parent(struct clk_hw *hw, u8 index)
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{
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struct flexgen *flexgen = to_flexgen(hw);
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struct clk_hw *mux_hw = &flexgen->mux.hw;
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__clk_hw_set_clk(mux_hw, hw);
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return clk_mux_ops.set_parent(mux_hw, index);
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}
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static inline unsigned long
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clk_best_div(unsigned long parent_rate, unsigned long rate)
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{
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return parent_rate / rate + ((rate > (2*(parent_rate % rate))) ? 0 : 1);
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}
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static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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unsigned long div;
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/* Round div according to exact prate and wished rate */
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div = clk_best_div(*prate, rate);
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
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*prate = rate * div;
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return rate;
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}
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return *prate / div;
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}
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static unsigned long flexgen_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct flexgen *flexgen = to_flexgen(hw);
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struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
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struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
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unsigned long mid_rate;
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__clk_hw_set_clk(pdiv_hw, hw);
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__clk_hw_set_clk(fdiv_hw, hw);
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mid_rate = clk_divider_ops.recalc_rate(pdiv_hw, parent_rate);
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return clk_divider_ops.recalc_rate(fdiv_hw, mid_rate);
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}
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static int flexgen_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct flexgen *flexgen = to_flexgen(hw);
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struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
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struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
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struct clk_hw *sync_hw = &flexgen->sync.hw;
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struct clk_gate *config = to_clk_gate(sync_hw);
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unsigned long div = 0;
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int ret = 0;
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u32 reg;
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__clk_hw_set_clk(pdiv_hw, hw);
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__clk_hw_set_clk(fdiv_hw, hw);
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if (flexgen->control_mode) {
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reg = readl(config->reg);
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reg &= ~BIT(config->bit_idx);
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writel(reg, config->reg);
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}
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div = clk_best_div(parent_rate, rate);
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/*
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* pdiv is mainly targeted for low freq results, while fdiv
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* should be used for div <= 64. The other way round can
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* lead to 'duty cycle' issues.
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*/
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if (div <= 64) {
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clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate);
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ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div);
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} else {
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clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate);
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ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div);
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}
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return ret;
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}
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static const struct clk_ops flexgen_ops = {
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.enable = flexgen_enable,
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.disable = flexgen_disable,
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.is_enabled = flexgen_is_enabled,
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.get_parent = flexgen_get_parent,
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.set_parent = flexgen_set_parent,
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.round_rate = flexgen_round_rate,
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.recalc_rate = flexgen_recalc_rate,
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.set_rate = flexgen_set_rate,
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};
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static struct clk *clk_register_flexgen(const char *name,
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const char **parent_names, u8 num_parents,
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void __iomem *reg, spinlock_t *lock, u32 idx,
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unsigned long flexgen_flags, bool mode) {
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struct flexgen *fgxbar;
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struct clk *clk;
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struct clk_init_data init;
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u32 xbar_shift;
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void __iomem *xbar_reg, *fdiv_reg;
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fgxbar = kzalloc(sizeof(struct flexgen), GFP_KERNEL);
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if (!fgxbar)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &flexgen_ops;
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init.flags = CLK_GET_RATE_NOCACHE | flexgen_flags;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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xbar_reg = reg + 0x18 + (idx & ~0x3);
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xbar_shift = (idx % 4) * 0x8;
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fdiv_reg = reg + 0x164 + idx * 4;
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/* Crossbar element config */
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fgxbar->mux.lock = lock;
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fgxbar->mux.mask = BIT(6) - 1;
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fgxbar->mux.reg = xbar_reg;
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fgxbar->mux.shift = xbar_shift;
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fgxbar->mux.table = NULL;
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/* Pre-divider's gate config (in xbar register)*/
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fgxbar->pgate.lock = lock;
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fgxbar->pgate.reg = xbar_reg;
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fgxbar->pgate.bit_idx = xbar_shift + 6;
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/* Pre-divider config */
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fgxbar->pdiv.lock = lock;
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fgxbar->pdiv.reg = reg + 0x58 + idx * 4;
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fgxbar->pdiv.width = 10;
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/* Final divider's gate config */
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fgxbar->fgate.lock = lock;
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fgxbar->fgate.reg = fdiv_reg;
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fgxbar->fgate.bit_idx = 6;
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/* Final divider config */
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fgxbar->fdiv.lock = lock;
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fgxbar->fdiv.reg = fdiv_reg;
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fgxbar->fdiv.width = 6;
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/* Final divider sync config */
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fgxbar->sync.lock = lock;
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fgxbar->sync.reg = fdiv_reg;
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fgxbar->sync.bit_idx = 7;
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fgxbar->control_mode = mode;
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fgxbar->hw.init = &init;
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clk = clk_register(NULL, &fgxbar->hw);
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if (IS_ERR(clk))
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kfree(fgxbar);
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else
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pr_debug("%s: parent %s rate %u\n",
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__clk_get_name(clk),
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__clk_get_name(clk_get_parent(clk)),
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(unsigned int)clk_get_rate(clk));
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return clk;
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}
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static const char ** __init flexgen_get_parents(struct device_node *np,
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int *num_parents)
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{
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const char **parents;
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unsigned int nparents;
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nparents = of_clk_get_parent_count(np);
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if (WARN_ON(!nparents))
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return NULL;
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parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
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if (!parents)
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return NULL;
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*num_parents = of_clk_parent_fill(np, parents, nparents);
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return parents;
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}
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static const struct clkgen_data clkgen_audio = {
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.flags = CLK_SET_RATE_PARENT,
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};
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static const struct clkgen_data clkgen_video = {
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.flags = CLK_SET_RATE_PARENT,
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.mode = 1,
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};
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static const struct clkgen_clk_out clkgen_stih407_a0_clk_out[] = {
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/* This clk needs to be on so that memory interface is accessible */
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{ .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
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};
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static const struct clkgen_data clkgen_stih407_a0 = {
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.outputs = clkgen_stih407_a0_clk_out,
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.outputs_nb = ARRAY_SIZE(clkgen_stih407_a0_clk_out),
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};
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static const struct clkgen_clk_out clkgen_stih410_a0_clk_out[] = {
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/* Those clks need to be on so that memory interface is accessible */
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{ .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
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{ .name = "clk-ic-lmi1", .flags = CLK_IS_CRITICAL },
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};
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static const struct clkgen_data clkgen_stih410_a0 = {
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.outputs = clkgen_stih410_a0_clk_out,
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.outputs_nb = ARRAY_SIZE(clkgen_stih410_a0_clk_out),
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};
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static const struct clkgen_clk_out clkgen_stih407_c0_clk_out[] = {
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{ .name = "clk-icn-gpu", },
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{ .name = "clk-fdma", },
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{ .name = "clk-nand", },
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{ .name = "clk-hva", },
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{ .name = "clk-proc-stfe", },
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{ .name = "clk-proc-tp", },
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{ .name = "clk-rx-icn-dmu", },
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{ .name = "clk-rx-icn-hva", },
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/* This clk needs to be on to keep bus interconnect alive */
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{ .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
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/* This clk needs to be on to keep bus interconnect alive */
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{ .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
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{ .name = "clk-mmc-0", },
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{ .name = "clk-mmc-1", },
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{ .name = "clk-jpegdec", },
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/* This clk needs to be on to keep A9 running */
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{ .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
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{ .name = "clk-ic-bdisp-0", },
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{ .name = "clk-ic-bdisp-1", },
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{ .name = "clk-pp-dmu", },
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{ .name = "clk-vid-dmu", },
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{ .name = "clk-dss-lpc", },
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{ .name = "clk-st231-aud-0", },
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{ .name = "clk-st231-gp-1", },
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{ .name = "clk-st231-dmu", },
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/* This clk needs to be on to keep bus interconnect alive */
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{ .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
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{ .name = "clk-tx-icn-disp-1", },
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/* This clk needs to be on to keep bus interconnect alive */
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{ .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
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{ .name = "clk-stfe-frc2", },
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{ .name = "clk-eth-phy", },
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{ .name = "clk-eth-ref-phyclk", },
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{ .name = "clk-flash-promip", },
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{ .name = "clk-main-disp", },
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{ .name = "clk-aux-disp", },
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{ .name = "clk-compo-dvp", },
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};
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static const struct clkgen_data clkgen_stih407_c0 = {
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.outputs = clkgen_stih407_c0_clk_out,
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.outputs_nb = ARRAY_SIZE(clkgen_stih407_c0_clk_out),
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};
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static const struct clkgen_clk_out clkgen_stih410_c0_clk_out[] = {
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{ .name = "clk-icn-gpu", },
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{ .name = "clk-fdma", },
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{ .name = "clk-nand", },
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{ .name = "clk-hva", },
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{ .name = "clk-proc-stfe", },
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{ .name = "clk-proc-tp", },
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{ .name = "clk-rx-icn-dmu", },
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{ .name = "clk-rx-icn-hva", },
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/* This clk needs to be on to keep bus interconnect alive */
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{ .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
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/* This clk needs to be on to keep bus interconnect alive */
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{ .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
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{ .name = "clk-mmc-0", },
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{ .name = "clk-mmc-1", },
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{ .name = "clk-jpegdec", },
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/* This clk needs to be on to keep A9 running */
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{ .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
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{ .name = "clk-ic-bdisp-0", },
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{ .name = "clk-ic-bdisp-1", },
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{ .name = "clk-pp-dmu", },
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{ .name = "clk-vid-dmu", },
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{ .name = "clk-dss-lpc", },
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{ .name = "clk-st231-aud-0", },
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{ .name = "clk-st231-gp-1", },
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{ .name = "clk-st231-dmu", },
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/* This clk needs to be on to keep bus interconnect alive */
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{ .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
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{ .name = "clk-tx-icn-disp-1", },
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/* This clk needs to be on to keep bus interconnect alive */
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{ .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
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{ .name = "clk-stfe-frc2", },
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{ .name = "clk-eth-phy", },
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{ .name = "clk-eth-ref-phyclk", },
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{ .name = "clk-flash-promip", },
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{ .name = "clk-main-disp", },
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{ .name = "clk-aux-disp", },
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{ .name = "clk-compo-dvp", },
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{ .name = "clk-tx-icn-hades", },
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{ .name = "clk-rx-icn-hades", },
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/* This clk needs to be on to keep bus interconnect alive */
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{ .name = "clk-icn-reg-16", .flags = CLK_IS_CRITICAL },
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{ .name = "clk-pp-hades", },
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{ .name = "clk-clust-hades", },
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{ .name = "clk-hwpe-hades", },
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{ .name = "clk-fc-hades", },
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};
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static const struct clkgen_data clkgen_stih410_c0 = {
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.outputs = clkgen_stih410_c0_clk_out,
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.outputs_nb = ARRAY_SIZE(clkgen_stih410_c0_clk_out),
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};
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static const struct clkgen_clk_out clkgen_stih418_c0_clk_out[] = {
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{ .name = "clk-icn-gpu", },
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{ .name = "clk-fdma", },
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{ .name = "clk-nand", },
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{ .name = "clk-hva", },
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{ .name = "clk-proc-stfe", },
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{ .name = "clk-tp", },
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/* This clk needs to be on to keep bus interconnect alive */
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{ .name = "clk-rx-icn-dmu", .flags = CLK_IS_CRITICAL },
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/* This clk needs to be on to keep bus interconnect alive */
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{ .name = "clk-rx-icn-hva", .flags = CLK_IS_CRITICAL },
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{ .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
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/* This clk needs to be on to keep bus interconnect alive */
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{ .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
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{ .name = "clk-mmc-0", },
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{ .name = "clk-mmc-1", },
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{ .name = "clk-jpegdec", },
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/* This clk needs to be on to keep bus interconnect alive */
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{ .name = "clk-icn-reg", .flags = CLK_IS_CRITICAL },
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{ .name = "clk-proc-bdisp-0", },
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{ .name = "clk-proc-bdisp-1", },
|
|
{ .name = "clk-pp-dmu", },
|
|
{ .name = "clk-vid-dmu", },
|
|
{ .name = "clk-dss-lpc", },
|
|
{ .name = "clk-st231-aud-0", },
|
|
{ .name = "clk-st231-gp-1", },
|
|
{ .name = "clk-st231-dmu", },
|
|
/* This clk needs to be on to keep bus interconnect alive */
|
|
{ .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
|
|
/* This clk needs to be on to keep bus interconnect alive */
|
|
{ .name = "clk-tx-icn-1", .flags = CLK_IS_CRITICAL },
|
|
/* This clk needs to be on to keep bus interconnect alive */
|
|
{ .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
|
|
{ .name = "clk-stfe-frc2", },
|
|
{ .name = "clk-eth-phyref", },
|
|
{ .name = "clk-eth-ref-phyclk", },
|
|
{ .name = "clk-flash-promip", },
|
|
{ .name = "clk-main-disp", },
|
|
{ .name = "clk-aux-disp", },
|
|
{ .name = "clk-compo-dvp", },
|
|
/* This clk needs to be on to keep bus interconnect alive */
|
|
{ .name = "clk-tx-icn-hades", .flags = CLK_IS_CRITICAL },
|
|
/* This clk needs to be on to keep bus interconnect alive */
|
|
{ .name = "clk-rx-icn-hades", .flags = CLK_IS_CRITICAL },
|
|
/* This clk needs to be on to keep bus interconnect alive */
|
|
{ .name = "clk-icn-reg-16", .flags = CLK_IS_CRITICAL },
|
|
{ .name = "clk-pp-hevc", },
|
|
{ .name = "clk-clust-hevc", },
|
|
{ .name = "clk-hwpe-hevc", },
|
|
{ .name = "clk-fc-hevc", },
|
|
{ .name = "clk-proc-mixer", },
|
|
{ .name = "clk-proc-sc", },
|
|
{ .name = "clk-avsp-hevc", },
|
|
};
|
|
|
|
static const struct clkgen_data clkgen_stih418_c0 = {
|
|
.outputs = clkgen_stih418_c0_clk_out,
|
|
.outputs_nb = ARRAY_SIZE(clkgen_stih418_c0_clk_out),
|
|
};
|
|
|
|
static const struct clkgen_clk_out clkgen_stih407_d0_clk_out[] = {
|
|
{ .name = "clk-pcm-0", },
|
|
{ .name = "clk-pcm-1", },
|
|
{ .name = "clk-pcm-2", },
|
|
{ .name = "clk-spdiff", },
|
|
};
|
|
|
|
static const struct clkgen_data clkgen_stih407_d0 = {
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.outputs = clkgen_stih407_d0_clk_out,
|
|
.outputs_nb = ARRAY_SIZE(clkgen_stih407_d0_clk_out),
|
|
};
|
|
|
|
static const struct clkgen_clk_out clkgen_stih410_d0_clk_out[] = {
|
|
{ .name = "clk-pcm-0", },
|
|
{ .name = "clk-pcm-1", },
|
|
{ .name = "clk-pcm-2", },
|
|
{ .name = "clk-spdiff", },
|
|
{ .name = "clk-pcmr10-master", },
|
|
{ .name = "clk-usb2-phy", },
|
|
};
|
|
|
|
static const struct clkgen_data clkgen_stih410_d0 = {
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.outputs = clkgen_stih410_d0_clk_out,
|
|
.outputs_nb = ARRAY_SIZE(clkgen_stih410_d0_clk_out),
|
|
};
|
|
|
|
static const struct clkgen_clk_out clkgen_stih407_d2_clk_out[] = {
|
|
{ .name = "clk-pix-main-disp", },
|
|
{ .name = "clk-pix-pip", },
|
|
{ .name = "clk-pix-gdp1", },
|
|
{ .name = "clk-pix-gdp2", },
|
|
{ .name = "clk-pix-gdp3", },
|
|
{ .name = "clk-pix-gdp4", },
|
|
{ .name = "clk-pix-aux-disp", },
|
|
{ .name = "clk-denc", },
|
|
{ .name = "clk-pix-hddac", },
|
|
{ .name = "clk-hddac", },
|
|
{ .name = "clk-sddac", },
|
|
{ .name = "clk-pix-dvo", },
|
|
{ .name = "clk-dvo", },
|
|
{ .name = "clk-pix-hdmi", },
|
|
{ .name = "clk-tmds-hdmi", },
|
|
{ .name = "clk-ref-hdmiphy", },
|
|
};
|
|
|
|
static const struct clkgen_data clkgen_stih407_d2 = {
|
|
.outputs = clkgen_stih407_d2_clk_out,
|
|
.outputs_nb = ARRAY_SIZE(clkgen_stih407_d2_clk_out),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.mode = 1,
|
|
};
|
|
|
|
static const struct clkgen_clk_out clkgen_stih418_d2_clk_out[] = {
|
|
{ .name = "clk-pix-main-disp", },
|
|
{ .name = "", },
|
|
{ .name = "", },
|
|
{ .name = "", },
|
|
{ .name = "", },
|
|
{ .name = "clk-tmds-hdmi-div2", },
|
|
{ .name = "clk-pix-aux-disp", },
|
|
{ .name = "clk-denc", },
|
|
{ .name = "clk-pix-hddac", },
|
|
{ .name = "clk-hddac", },
|
|
{ .name = "clk-sddac", },
|
|
{ .name = "clk-pix-dvo", },
|
|
{ .name = "clk-dvo", },
|
|
{ .name = "clk-pix-hdmi", },
|
|
{ .name = "clk-tmds-hdmi", },
|
|
{ .name = "clk-ref-hdmiphy", },
|
|
{ .name = "", }, { .name = "", }, { .name = "", }, { .name = "", },
|
|
{ .name = "", }, { .name = "", }, { .name = "", }, { .name = "", },
|
|
{ .name = "", }, { .name = "", }, { .name = "", }, { .name = "", },
|
|
{ .name = "", }, { .name = "", }, { .name = "", }, { .name = "", },
|
|
{ .name = "", }, { .name = "", }, { .name = "", }, { .name = "", },
|
|
{ .name = "", }, { .name = "", }, { .name = "", }, { .name = "", },
|
|
{ .name = "", }, { .name = "", }, { .name = "", }, { .name = "", },
|
|
{ .name = "", }, { .name = "", }, { .name = "", },
|
|
{ .name = "clk-vp9", },
|
|
};
|
|
|
|
static const struct clkgen_data clkgen_stih418_d2 = {
|
|
.outputs = clkgen_stih418_d2_clk_out,
|
|
.outputs_nb = ARRAY_SIZE(clkgen_stih418_d2_clk_out),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.mode = 1,
|
|
};
|
|
|
|
static const struct clkgen_clk_out clkgen_stih407_d3_clk_out[] = {
|
|
{ .name = "clk-stfe-frc1", },
|
|
{ .name = "clk-tsout-0", },
|
|
{ .name = "clk-tsout-1", },
|
|
{ .name = "clk-mchi", },
|
|
{ .name = "clk-vsens-compo", },
|
|
{ .name = "clk-frc1-remote", },
|
|
{ .name = "clk-lpc-0", },
|
|
{ .name = "clk-lpc-1", },
|
|
};
|
|
|
|
static const struct clkgen_data clkgen_stih407_d3 = {
|
|
.outputs = clkgen_stih407_d3_clk_out,
|
|
.outputs_nb = ARRAY_SIZE(clkgen_stih407_d3_clk_out),
|
|
};
|
|
|
|
static const struct of_device_id flexgen_of_match[] = {
|
|
{
|
|
.compatible = "st,flexgen-audio",
|
|
.data = &clkgen_audio,
|
|
},
|
|
{
|
|
.compatible = "st,flexgen-video",
|
|
.data = &clkgen_video,
|
|
},
|
|
{
|
|
.compatible = "st,flexgen-stih407-a0",
|
|
.data = &clkgen_stih407_a0,
|
|
},
|
|
{
|
|
.compatible = "st,flexgen-stih410-a0",
|
|
.data = &clkgen_stih410_a0,
|
|
},
|
|
{
|
|
.compatible = "st,flexgen-stih407-c0",
|
|
.data = &clkgen_stih407_c0,
|
|
},
|
|
{
|
|
.compatible = "st,flexgen-stih410-c0",
|
|
.data = &clkgen_stih410_c0,
|
|
},
|
|
{
|
|
.compatible = "st,flexgen-stih418-c0",
|
|
.data = &clkgen_stih418_c0,
|
|
},
|
|
{
|
|
.compatible = "st,flexgen-stih407-d0",
|
|
.data = &clkgen_stih407_d0,
|
|
},
|
|
{
|
|
.compatible = "st,flexgen-stih410-d0",
|
|
.data = &clkgen_stih410_d0,
|
|
},
|
|
{
|
|
.compatible = "st,flexgen-stih407-d2",
|
|
.data = &clkgen_stih407_d2,
|
|
},
|
|
{
|
|
.compatible = "st,flexgen-stih418-d2",
|
|
.data = &clkgen_stih418_d2,
|
|
},
|
|
{
|
|
.compatible = "st,flexgen-stih407-d3",
|
|
.data = &clkgen_stih407_d3,
|
|
},
|
|
{}
|
|
};
|
|
|
|
static void __init st_of_flexgen_setup(struct device_node *np)
|
|
{
|
|
struct device_node *pnode;
|
|
void __iomem *reg;
|
|
struct clk_onecell_data *clk_data;
|
|
const char **parents;
|
|
int num_parents, i;
|
|
spinlock_t *rlock = NULL;
|
|
const struct of_device_id *match;
|
|
struct clkgen_data *data = NULL;
|
|
unsigned long flex_flags = 0;
|
|
int ret;
|
|
bool clk_mode = 0;
|
|
const char *clk_name;
|
|
|
|
pnode = of_get_parent(np);
|
|
if (!pnode)
|
|
return;
|
|
|
|
reg = of_iomap(pnode, 0);
|
|
of_node_put(pnode);
|
|
if (!reg)
|
|
return;
|
|
|
|
parents = flexgen_get_parents(np, &num_parents);
|
|
if (!parents) {
|
|
iounmap(reg);
|
|
return;
|
|
}
|
|
|
|
match = of_match_node(flexgen_of_match, np);
|
|
if (match) {
|
|
data = (struct clkgen_data *)match->data;
|
|
flex_flags = data->flags;
|
|
clk_mode = data->mode;
|
|
}
|
|
|
|
clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
|
|
if (!clk_data)
|
|
goto err;
|
|
|
|
/* First try to get output information from the compatible data */
|
|
if (!data || !data->outputs_nb || !data->outputs) {
|
|
ret = of_property_count_strings(np, "clock-output-names");
|
|
if (ret <= 0) {
|
|
pr_err("%s: Failed to get number of output clocks (%d)",
|
|
__func__, clk_data->clk_num);
|
|
goto err;
|
|
}
|
|
clk_data->clk_num = ret;
|
|
} else
|
|
clk_data->clk_num = data->outputs_nb;
|
|
|
|
clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
|
|
GFP_KERNEL);
|
|
if (!clk_data->clks)
|
|
goto err;
|
|
|
|
rlock = kzalloc(sizeof(spinlock_t), GFP_KERNEL);
|
|
if (!rlock)
|
|
goto err;
|
|
|
|
spin_lock_init(rlock);
|
|
|
|
for (i = 0; i < clk_data->clk_num; i++) {
|
|
struct clk *clk;
|
|
|
|
if (!data || !data->outputs_nb || !data->outputs) {
|
|
if (of_property_read_string_index(np,
|
|
"clock-output-names",
|
|
i, &clk_name))
|
|
break;
|
|
flex_flags &= ~CLK_IS_CRITICAL;
|
|
of_clk_detect_critical(np, i, &flex_flags);
|
|
} else {
|
|
clk_name = data->outputs[i].name;
|
|
flex_flags = data->flags | data->outputs[i].flags;
|
|
}
|
|
|
|
/*
|
|
* If we read an empty clock name then the output is unused
|
|
*/
|
|
if (*clk_name == '\0')
|
|
continue;
|
|
|
|
clk = clk_register_flexgen(clk_name, parents, num_parents,
|
|
reg, rlock, i, flex_flags, clk_mode);
|
|
|
|
if (IS_ERR(clk))
|
|
goto err;
|
|
|
|
clk_data->clks[i] = clk;
|
|
}
|
|
|
|
kfree(parents);
|
|
of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
|
|
|
|
return;
|
|
|
|
err:
|
|
iounmap(reg);
|
|
if (clk_data)
|
|
kfree(clk_data->clks);
|
|
kfree(clk_data);
|
|
kfree(parents);
|
|
kfree(rlock);
|
|
}
|
|
CLK_OF_DECLARE(flexgen, "st,flexgen", st_of_flexgen_setup);
|