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![Gabriel Fernandez](/assets/img/avatar_default.png)
Some muxes need to set a the safe position when clock is off. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-12-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
188 lines
4.7 KiB
C
188 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
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* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
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*/
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#include <linux/clk-provider.h>
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struct stm32_rcc_match_data;
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struct stm32_mux_cfg {
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u16 offset;
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u8 shift;
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u8 width;
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u8 flags;
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u32 *table;
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u8 ready;
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};
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struct stm32_gate_cfg {
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u16 offset;
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u8 bit_idx;
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u8 set_clr;
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};
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struct stm32_div_cfg {
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u16 offset;
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u8 shift;
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u8 width;
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u8 flags;
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u8 ready;
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const struct clk_div_table *table;
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};
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struct stm32_composite_cfg {
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int mux;
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int gate;
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int div;
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};
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#define NO_ID 0xFFFFFFFF
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#define NO_STM32_MUX 0xFFFF
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#define NO_STM32_DIV 0xFFFF
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#define NO_STM32_GATE 0xFFFF
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struct clock_config {
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unsigned long id;
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int sec_id;
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void *clock_cfg;
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struct clk_hw *(*func)(struct device *dev,
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const struct stm32_rcc_match_data *data,
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void __iomem *base,
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spinlock_t *lock,
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const struct clock_config *cfg);
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};
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struct clk_stm32_clock_data {
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u16 *gate_cpt;
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const struct stm32_gate_cfg *gates;
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const struct stm32_mux_cfg *muxes;
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const struct stm32_div_cfg *dividers;
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struct clk_hw *(*is_multi_mux)(struct clk_hw *hw);
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};
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struct stm32_rcc_match_data {
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struct clk_hw_onecell_data *hw_clks;
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unsigned int num_clocks;
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const struct clock_config *tab_clocks;
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unsigned int maxbinding;
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struct clk_stm32_clock_data *clock_data;
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u32 clear_offset;
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int (*check_security)(void __iomem *base,
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const struct clock_config *cfg);
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int (*multi_mux)(void __iomem *base, const struct clock_config *cfg);
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};
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int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
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void __iomem *base);
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int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
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void __iomem *base);
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/* MUX define */
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#define MUX_NO_RDY 0xFF
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#define MUX_SAFE BIT(7)
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/* DIV define */
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#define DIV_NO_RDY 0xFF
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/* Definition of clock structure */
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struct clk_stm32_mux {
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u16 mux_id;
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struct clk_hw hw;
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void __iomem *base;
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struct clk_stm32_clock_data *clock_data;
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spinlock_t *lock; /* spin lock */
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};
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#define to_clk_stm32_mux(_hw) container_of(_hw, struct clk_stm32_mux, hw)
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struct clk_stm32_gate {
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u16 gate_id;
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struct clk_hw hw;
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void __iomem *base;
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struct clk_stm32_clock_data *clock_data;
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spinlock_t *lock; /* spin lock */
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};
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#define to_clk_stm32_gate(_hw) container_of(_hw, struct clk_stm32_gate, hw)
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struct clk_stm32_div {
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u16 div_id;
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struct clk_hw hw;
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void __iomem *base;
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struct clk_stm32_clock_data *clock_data;
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spinlock_t *lock; /* spin lock */
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};
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#define to_clk_stm32_divider(_hw) container_of(_hw, struct clk_stm32_div, hw)
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struct clk_stm32_composite {
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u16 gate_id;
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u16 mux_id;
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u16 div_id;
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struct clk_hw hw;
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void __iomem *base;
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struct clk_stm32_clock_data *clock_data;
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spinlock_t *lock; /* spin lock */
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};
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#define to_clk_stm32_composite(_hw) container_of(_hw, struct clk_stm32_composite, hw)
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/* Clock operators */
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extern const struct clk_ops clk_stm32_mux_ops;
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extern const struct clk_ops clk_stm32_gate_ops;
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extern const struct clk_ops clk_stm32_divider_ops;
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extern const struct clk_ops clk_stm32_composite_ops;
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/* Clock registering */
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struct clk_hw *clk_stm32_mux_register(struct device *dev,
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const struct stm32_rcc_match_data *data,
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void __iomem *base,
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spinlock_t *lock,
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const struct clock_config *cfg);
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struct clk_hw *clk_stm32_gate_register(struct device *dev,
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const struct stm32_rcc_match_data *data,
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void __iomem *base,
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spinlock_t *lock,
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const struct clock_config *cfg);
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struct clk_hw *clk_stm32_div_register(struct device *dev,
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const struct stm32_rcc_match_data *data,
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void __iomem *base,
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spinlock_t *lock,
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const struct clock_config *cfg);
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struct clk_hw *clk_stm32_composite_register(struct device *dev,
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const struct stm32_rcc_match_data *data,
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void __iomem *base,
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spinlock_t *lock,
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const struct clock_config *cfg);
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#define STM32_CLOCK_CFG(_binding, _clk, _sec_id, _struct, _register)\
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{\
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.id = (_binding),\
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.sec_id = (_sec_id),\
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.clock_cfg = (_struct) {_clk},\
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.func = (_register),\
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}
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#define STM32_MUX_CFG(_binding, _clk, _sec_id)\
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STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_mux *,\
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&clk_stm32_mux_register)
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#define STM32_GATE_CFG(_binding, _clk, _sec_id)\
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STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_gate *,\
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&clk_stm32_gate_register)
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#define STM32_DIV_CFG(_binding, _clk, _sec_id)\
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STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_div *,\
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&clk_stm32_div_register)
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#define STM32_COMPOSITE_CFG(_binding, _clk, _sec_id)\
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STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_composite *,\
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&clk_stm32_composite_register)
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