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![Kunihiko Hayashi](/assets/img/avatar_default.png)
Add SoC-glue clock source selector for ahci controller on UniPhier SoCs. Currently this supports Pro4 only. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1634000035-3114-6-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
229 lines
5.6 KiB
C
229 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/init.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-uniphier.h"
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static struct clk_hw *uniphier_clk_register(struct device *dev,
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struct regmap *regmap,
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const struct uniphier_clk_data *data)
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{
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switch (data->type) {
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case UNIPHIER_CLK_TYPE_CPUGEAR:
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return uniphier_clk_register_cpugear(dev, regmap, data->name,
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&data->data.cpugear);
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case UNIPHIER_CLK_TYPE_FIXED_FACTOR:
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return uniphier_clk_register_fixed_factor(dev, data->name,
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&data->data.factor);
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case UNIPHIER_CLK_TYPE_FIXED_RATE:
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return uniphier_clk_register_fixed_rate(dev, data->name,
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&data->data.rate);
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case UNIPHIER_CLK_TYPE_GATE:
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return uniphier_clk_register_gate(dev, regmap, data->name,
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&data->data.gate);
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case UNIPHIER_CLK_TYPE_MUX:
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return uniphier_clk_register_mux(dev, regmap, data->name,
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&data->data.mux);
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default:
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dev_err(dev, "unsupported clock type\n");
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return ERR_PTR(-EINVAL);
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}
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}
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static int uniphier_clk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct clk_hw_onecell_data *hw_data;
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const struct uniphier_clk_data *p, *data;
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struct regmap *regmap;
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struct device_node *parent;
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int clk_num = 0;
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data = of_device_get_match_data(dev);
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if (WARN_ON(!data))
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return -EINVAL;
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parent = of_get_parent(dev->of_node); /* parent should be syscon node */
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regmap = syscon_node_to_regmap(parent);
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of_node_put(parent);
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if (IS_ERR(regmap)) {
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dev_err(dev, "failed to get regmap (error %ld)\n",
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PTR_ERR(regmap));
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return PTR_ERR(regmap);
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}
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for (p = data; p->name; p++)
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clk_num = max(clk_num, p->idx + 1);
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hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, clk_num),
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GFP_KERNEL);
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if (!hw_data)
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return -ENOMEM;
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hw_data->num = clk_num;
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/* avoid returning NULL for unused idx */
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while (--clk_num >= 0)
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hw_data->hws[clk_num] = ERR_PTR(-EINVAL);
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for (p = data; p->name; p++) {
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struct clk_hw *hw;
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dev_dbg(dev, "register %s (index=%d)\n", p->name, p->idx);
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hw = uniphier_clk_register(dev, regmap, p);
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if (WARN(IS_ERR(hw), "failed to register %s", p->name))
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continue;
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if (p->idx >= 0)
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hw_data->hws[p->idx] = hw;
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}
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return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
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hw_data);
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}
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static int uniphier_clk_remove(struct platform_device *pdev)
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{
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of_clk_del_provider(pdev->dev.of_node);
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return 0;
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}
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static const struct of_device_id uniphier_clk_match[] = {
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/* System clock */
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{
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.compatible = "socionext,uniphier-ld4-clock",
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.data = uniphier_ld4_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro4-clock",
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.data = uniphier_pro4_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-sld8-clock",
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.data = uniphier_sld8_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro5-clock",
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.data = uniphier_pro5_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pxs2-clock",
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.data = uniphier_pxs2_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld11-clock",
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.data = uniphier_ld11_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld20-clock",
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.data = uniphier_ld20_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pxs3-clock",
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.data = uniphier_pxs3_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-nx1-clock",
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.data = uniphier_nx1_sys_clk_data,
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},
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/* Media I/O clock, SD clock */
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{
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.compatible = "socionext,uniphier-ld4-mio-clock",
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.data = uniphier_ld4_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro4-mio-clock",
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.data = uniphier_ld4_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-sld8-mio-clock",
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.data = uniphier_ld4_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro5-sd-clock",
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.data = uniphier_pro5_sd_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pxs2-sd-clock",
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.data = uniphier_pro5_sd_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld11-mio-clock",
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.data = uniphier_ld4_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld20-sd-clock",
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.data = uniphier_pro5_sd_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pxs3-sd-clock",
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.data = uniphier_pro5_sd_clk_data,
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},
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{
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.compatible = "socionext,uniphier-nx1-sd-clock",
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.data = uniphier_pro5_sd_clk_data,
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},
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/* Peripheral clock */
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{
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.compatible = "socionext,uniphier-ld4-peri-clock",
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.data = uniphier_ld4_peri_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro4-peri-clock",
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.data = uniphier_pro4_peri_clk_data,
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},
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{
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.compatible = "socionext,uniphier-sld8-peri-clock",
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.data = uniphier_ld4_peri_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro5-peri-clock",
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.data = uniphier_pro4_peri_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pxs2-peri-clock",
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.data = uniphier_pro4_peri_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld11-peri-clock",
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.data = uniphier_pro4_peri_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld20-peri-clock",
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.data = uniphier_pro4_peri_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pxs3-peri-clock",
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.data = uniphier_pro4_peri_clk_data,
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},
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{
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.compatible = "socionext,uniphier-nx1-peri-clock",
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.data = uniphier_pro4_peri_clk_data,
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},
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/* SoC-glue clock */
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{
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.compatible = "socionext,uniphier-pro4-sg-clock",
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.data = uniphier_pro4_sg_clk_data,
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},
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{ /* sentinel */ }
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};
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static struct platform_driver uniphier_clk_driver = {
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.probe = uniphier_clk_probe,
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.remove = uniphier_clk_remove,
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.driver = {
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.name = "uniphier-clk",
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.of_match_table = uniphier_clk_match,
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},
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};
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builtin_platform_driver(uniphier_clk_driver);
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