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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 263 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141901.208660670@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
390 lines
8.8 KiB
C
390 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Intel Atom platform clocks driver for BayTrail and CherryTrail SoCs
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*
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* Copyright (C) 2016, Intel Corporation
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* Author: Irina Tirdea <irina.tirdea@intel.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_data/x86/clk-pmc-atom.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#define PLT_CLK_NAME_BASE "pmc_plt_clk"
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#define PMC_CLK_CTL_OFFSET 0x60
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#define PMC_CLK_CTL_SIZE 4
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#define PMC_CLK_NUM 6
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#define PMC_CLK_CTL_GATED_ON_D3 0x0
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#define PMC_CLK_CTL_FORCE_ON 0x1
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#define PMC_CLK_CTL_FORCE_OFF 0x2
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#define PMC_CLK_CTL_RESERVED 0x3
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#define PMC_MASK_CLK_CTL GENMASK(1, 0)
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#define PMC_MASK_CLK_FREQ BIT(2)
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#define PMC_CLK_FREQ_XTAL (0 << 2) /* 25 MHz */
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#define PMC_CLK_FREQ_PLL (1 << 2) /* 19.2 MHz */
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struct clk_plt_fixed {
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struct clk_hw *clk;
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struct clk_lookup *lookup;
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};
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struct clk_plt {
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struct clk_hw hw;
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void __iomem *reg;
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struct clk_lookup *lookup;
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/* protect access to PMC registers */
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spinlock_t lock;
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};
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#define to_clk_plt(_hw) container_of(_hw, struct clk_plt, hw)
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struct clk_plt_data {
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struct clk_plt_fixed **parents;
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u8 nparents;
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struct clk_plt *clks[PMC_CLK_NUM];
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struct clk_lookup *mclk_lookup;
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struct clk_lookup *ether_clk_lookup;
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};
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/* Return an index in parent table */
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static inline int plt_reg_to_parent(int reg)
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{
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switch (reg & PMC_MASK_CLK_FREQ) {
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default:
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case PMC_CLK_FREQ_XTAL:
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return 0;
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case PMC_CLK_FREQ_PLL:
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return 1;
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}
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}
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/* Return clk index of parent */
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static inline int plt_parent_to_reg(int index)
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{
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switch (index) {
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default:
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case 0:
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return PMC_CLK_FREQ_XTAL;
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case 1:
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return PMC_CLK_FREQ_PLL;
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}
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}
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/* Abstract status in simpler enabled/disabled value */
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static inline int plt_reg_to_enabled(int reg)
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{
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switch (reg & PMC_MASK_CLK_CTL) {
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case PMC_CLK_CTL_GATED_ON_D3:
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case PMC_CLK_CTL_FORCE_ON:
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return 1; /* enabled */
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case PMC_CLK_CTL_FORCE_OFF:
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case PMC_CLK_CTL_RESERVED:
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default:
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return 0; /* disabled */
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}
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}
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static void plt_clk_reg_update(struct clk_plt *clk, u32 mask, u32 val)
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{
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u32 tmp;
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unsigned long flags;
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spin_lock_irqsave(&clk->lock, flags);
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tmp = readl(clk->reg);
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tmp = (tmp & ~mask) | (val & mask);
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writel(tmp, clk->reg);
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spin_unlock_irqrestore(&clk->lock, flags);
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}
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static int plt_clk_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_plt *clk = to_clk_plt(hw);
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plt_clk_reg_update(clk, PMC_MASK_CLK_FREQ, plt_parent_to_reg(index));
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return 0;
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}
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static u8 plt_clk_get_parent(struct clk_hw *hw)
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{
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struct clk_plt *clk = to_clk_plt(hw);
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u32 value;
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value = readl(clk->reg);
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return plt_reg_to_parent(value);
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}
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static int plt_clk_enable(struct clk_hw *hw)
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{
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struct clk_plt *clk = to_clk_plt(hw);
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plt_clk_reg_update(clk, PMC_MASK_CLK_CTL, PMC_CLK_CTL_FORCE_ON);
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return 0;
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}
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static void plt_clk_disable(struct clk_hw *hw)
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{
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struct clk_plt *clk = to_clk_plt(hw);
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plt_clk_reg_update(clk, PMC_MASK_CLK_CTL, PMC_CLK_CTL_FORCE_OFF);
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}
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static int plt_clk_is_enabled(struct clk_hw *hw)
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{
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struct clk_plt *clk = to_clk_plt(hw);
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u32 value;
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value = readl(clk->reg);
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return plt_reg_to_enabled(value);
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}
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static const struct clk_ops plt_clk_ops = {
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.enable = plt_clk_enable,
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.disable = plt_clk_disable,
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.is_enabled = plt_clk_is_enabled,
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.get_parent = plt_clk_get_parent,
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.set_parent = plt_clk_set_parent,
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.determine_rate = __clk_mux_determine_rate,
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};
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static struct clk_plt *plt_clk_register(struct platform_device *pdev, int id,
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const struct pmc_clk_data *pmc_data,
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const char **parent_names,
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int num_parents)
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{
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struct clk_plt *pclk;
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struct clk_init_data init;
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int ret;
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pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL);
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if (!pclk)
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return ERR_PTR(-ENOMEM);
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init.name = kasprintf(GFP_KERNEL, "%s_%d", PLT_CLK_NAME_BASE, id);
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init.ops = &plt_clk_ops;
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init.flags = 0;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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pclk->hw.init = &init;
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pclk->reg = pmc_data->base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE;
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spin_lock_init(&pclk->lock);
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/*
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* On some systems, the pmc_plt_clocks already enabled by the
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* firmware are being marked as critical to avoid them being
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* gated by the clock framework.
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*/
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if (pmc_data->critical && plt_clk_is_enabled(&pclk->hw))
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init.flags |= CLK_IS_CRITICAL;
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ret = devm_clk_hw_register(&pdev->dev, &pclk->hw);
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if (ret) {
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pclk = ERR_PTR(ret);
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goto err_free_init;
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}
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pclk->lookup = clkdev_hw_create(&pclk->hw, init.name, NULL);
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if (!pclk->lookup) {
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pclk = ERR_PTR(-ENOMEM);
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goto err_free_init;
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}
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err_free_init:
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kfree(init.name);
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return pclk;
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}
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static void plt_clk_unregister(struct clk_plt *pclk)
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{
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clkdev_drop(pclk->lookup);
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}
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static struct clk_plt_fixed *plt_clk_register_fixed_rate(struct platform_device *pdev,
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const char *name,
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const char *parent_name,
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unsigned long fixed_rate)
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{
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struct clk_plt_fixed *pclk;
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pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL);
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if (!pclk)
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return ERR_PTR(-ENOMEM);
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pclk->clk = clk_hw_register_fixed_rate(&pdev->dev, name, parent_name,
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0, fixed_rate);
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if (IS_ERR(pclk->clk))
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return ERR_CAST(pclk->clk);
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pclk->lookup = clkdev_hw_create(pclk->clk, name, NULL);
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if (!pclk->lookup) {
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clk_hw_unregister_fixed_rate(pclk->clk);
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return ERR_PTR(-ENOMEM);
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}
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return pclk;
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}
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static void plt_clk_unregister_fixed_rate(struct clk_plt_fixed *pclk)
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{
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clkdev_drop(pclk->lookup);
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clk_hw_unregister_fixed_rate(pclk->clk);
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}
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static void plt_clk_unregister_fixed_rate_loop(struct clk_plt_data *data,
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unsigned int i)
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{
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while (i--)
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plt_clk_unregister_fixed_rate(data->parents[i]);
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}
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static void plt_clk_free_parent_names_loop(const char **parent_names,
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unsigned int i)
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{
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while (i--)
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kfree_const(parent_names[i]);
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kfree(parent_names);
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}
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static void plt_clk_unregister_loop(struct clk_plt_data *data,
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unsigned int i)
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{
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while (i--)
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plt_clk_unregister(data->clks[i]);
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}
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static const char **plt_clk_register_parents(struct platform_device *pdev,
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struct clk_plt_data *data,
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const struct pmc_clk *clks)
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{
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const char **parent_names;
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unsigned int i;
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int err;
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int nparents = 0;
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data->nparents = 0;
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while (clks[nparents].name)
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nparents++;
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data->parents = devm_kcalloc(&pdev->dev, nparents,
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sizeof(*data->parents), GFP_KERNEL);
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if (!data->parents)
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return ERR_PTR(-ENOMEM);
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parent_names = kcalloc(nparents, sizeof(*parent_names),
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GFP_KERNEL);
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if (!parent_names)
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return ERR_PTR(-ENOMEM);
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for (i = 0; i < nparents; i++) {
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data->parents[i] =
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plt_clk_register_fixed_rate(pdev, clks[i].name,
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clks[i].parent_name,
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clks[i].freq);
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if (IS_ERR(data->parents[i])) {
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err = PTR_ERR(data->parents[i]);
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goto err_unreg;
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}
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parent_names[i] = kstrdup_const(clks[i].name, GFP_KERNEL);
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}
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data->nparents = nparents;
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return parent_names;
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err_unreg:
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plt_clk_unregister_fixed_rate_loop(data, i);
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plt_clk_free_parent_names_loop(parent_names, i);
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return ERR_PTR(err);
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}
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static void plt_clk_unregister_parents(struct clk_plt_data *data)
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{
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plt_clk_unregister_fixed_rate_loop(data, data->nparents);
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}
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static int plt_clk_probe(struct platform_device *pdev)
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{
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const struct pmc_clk_data *pmc_data;
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const char **parent_names;
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struct clk_plt_data *data;
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unsigned int i;
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int err;
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pmc_data = dev_get_platdata(&pdev->dev);
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if (!pmc_data || !pmc_data->clks)
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return -EINVAL;
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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parent_names = plt_clk_register_parents(pdev, data, pmc_data->clks);
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if (IS_ERR(parent_names))
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return PTR_ERR(parent_names);
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for (i = 0; i < PMC_CLK_NUM; i++) {
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data->clks[i] = plt_clk_register(pdev, i, pmc_data,
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parent_names, data->nparents);
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if (IS_ERR(data->clks[i])) {
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err = PTR_ERR(data->clks[i]);
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goto err_unreg_clk_plt;
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}
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}
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data->mclk_lookup = clkdev_hw_create(&data->clks[3]->hw, "mclk", NULL);
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if (!data->mclk_lookup) {
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err = -ENOMEM;
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goto err_unreg_clk_plt;
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}
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data->ether_clk_lookup = clkdev_hw_create(&data->clks[4]->hw,
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"ether_clk", NULL);
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if (!data->ether_clk_lookup) {
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err = -ENOMEM;
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goto err_drop_mclk;
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}
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plt_clk_free_parent_names_loop(parent_names, data->nparents);
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platform_set_drvdata(pdev, data);
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return 0;
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err_drop_mclk:
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clkdev_drop(data->mclk_lookup);
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err_unreg_clk_plt:
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plt_clk_unregister_loop(data, i);
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plt_clk_unregister_parents(data);
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plt_clk_free_parent_names_loop(parent_names, data->nparents);
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return err;
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}
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static int plt_clk_remove(struct platform_device *pdev)
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{
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struct clk_plt_data *data;
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data = platform_get_drvdata(pdev);
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clkdev_drop(data->ether_clk_lookup);
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clkdev_drop(data->mclk_lookup);
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plt_clk_unregister_loop(data, PMC_CLK_NUM);
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plt_clk_unregister_parents(data);
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return 0;
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}
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static struct platform_driver plt_clk_driver = {
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.driver = {
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.name = "clk-pmc-atom",
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},
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.probe = plt_clk_probe,
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.remove = plt_clk_remove,
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};
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builtin_platform_driver(plt_clk_driver);
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