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![Meenakshi Aggarwal](/assets/img/avatar_default.png)
Add support for random number generation using PRNG mode of CAAM and expose the interface through crypto API. According to the RM, the HW implementation of the DRBG follows NIST SP 800-90A specification for DRBG_Hash SHA-256 function Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Horia Geant <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
235 lines
4.9 KiB
C
235 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Driver to expose SEC4 PRNG via crypto RNG API
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*
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* Copyright 2022 NXP
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*
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*/
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#include <linux/completion.h>
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#include <crypto/internal/rng.h>
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#include "compat.h"
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#include "regs.h"
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#include "intern.h"
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#include "desc_constr.h"
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#include "jr.h"
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#include "error.h"
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/*
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* Length of used descriptors, see caam_init_desc()
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*/
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#define CAAM_PRNG_MAX_DESC_LEN (CAAM_CMD_SZ + \
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CAAM_CMD_SZ + \
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CAAM_CMD_SZ + CAAM_PTR_SZ_MAX)
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/* prng per-device context */
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struct caam_prng_ctx {
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int err;
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struct completion done;
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};
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struct caam_prng_alg {
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struct rng_alg rng;
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bool registered;
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};
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static void caam_prng_done(struct device *jrdev, u32 *desc, u32 err,
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void *context)
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{
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struct caam_prng_ctx *jctx = context;
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jctx->err = err ? caam_jr_strstatus(jrdev, err) : 0;
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complete(&jctx->done);
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}
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static u32 *caam_init_reseed_desc(u32 *desc)
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{
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init_job_desc(desc, 0); /* + 1 cmd_sz */
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/* Generate random bytes: + 1 cmd_sz */
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append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
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OP_ALG_AS_FINALIZE);
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print_hex_dump_debug("prng reseed desc@: ", DUMP_PREFIX_ADDRESS,
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16, 4, desc, desc_bytes(desc), 1);
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return desc;
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}
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static u32 *caam_init_prng_desc(u32 *desc, dma_addr_t dst_dma, u32 len)
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{
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init_job_desc(desc, 0); /* + 1 cmd_sz */
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/* Generate random bytes: + 1 cmd_sz */
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append_operation(desc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG);
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/* Store bytes: + 1 cmd_sz + caam_ptr_sz */
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append_fifo_store(desc, dst_dma,
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len, FIFOST_TYPE_RNGSTORE);
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print_hex_dump_debug("prng job desc@: ", DUMP_PREFIX_ADDRESS,
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16, 4, desc, desc_bytes(desc), 1);
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return desc;
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}
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static int caam_prng_generate(struct crypto_rng *tfm,
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const u8 *src, unsigned int slen,
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u8 *dst, unsigned int dlen)
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{
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struct caam_prng_ctx ctx;
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struct device *jrdev;
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dma_addr_t dst_dma;
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u32 *desc;
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u8 *buf;
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int ret;
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buf = kzalloc(dlen, GFP_KERNEL);
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if (!buf)
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return -ENOMEM;
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jrdev = caam_jr_alloc();
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ret = PTR_ERR_OR_ZERO(jrdev);
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if (ret) {
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pr_err("Job Ring Device allocation failed\n");
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kfree(buf);
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return ret;
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}
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desc = kzalloc(CAAM_PRNG_MAX_DESC_LEN, GFP_KERNEL | GFP_DMA);
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if (!desc) {
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ret = -ENOMEM;
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goto out1;
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}
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dst_dma = dma_map_single(jrdev, buf, dlen, DMA_FROM_DEVICE);
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if (dma_mapping_error(jrdev, dst_dma)) {
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dev_err(jrdev, "Failed to map destination buffer memory\n");
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ret = -ENOMEM;
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goto out;
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}
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init_completion(&ctx.done);
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ret = caam_jr_enqueue(jrdev,
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caam_init_prng_desc(desc, dst_dma, dlen),
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caam_prng_done, &ctx);
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if (ret == -EINPROGRESS) {
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wait_for_completion(&ctx.done);
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ret = ctx.err;
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}
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dma_unmap_single(jrdev, dst_dma, dlen, DMA_FROM_DEVICE);
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if (!ret)
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memcpy(dst, buf, dlen);
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out:
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kfree(desc);
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out1:
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caam_jr_free(jrdev);
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kfree(buf);
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return ret;
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}
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static void caam_prng_exit(struct crypto_tfm *tfm) {}
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static int caam_prng_init(struct crypto_tfm *tfm)
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{
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return 0;
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}
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static int caam_prng_seed(struct crypto_rng *tfm,
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const u8 *seed, unsigned int slen)
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{
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struct caam_prng_ctx ctx;
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struct device *jrdev;
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u32 *desc;
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int ret;
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if (slen) {
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pr_err("Seed length should be zero\n");
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return -EINVAL;
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}
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jrdev = caam_jr_alloc();
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ret = PTR_ERR_OR_ZERO(jrdev);
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if (ret) {
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pr_err("Job Ring Device allocation failed\n");
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return ret;
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}
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desc = kzalloc(CAAM_PRNG_MAX_DESC_LEN, GFP_KERNEL | GFP_DMA);
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if (!desc) {
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caam_jr_free(jrdev);
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return -ENOMEM;
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}
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init_completion(&ctx.done);
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ret = caam_jr_enqueue(jrdev,
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caam_init_reseed_desc(desc),
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caam_prng_done, &ctx);
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if (ret == -EINPROGRESS) {
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wait_for_completion(&ctx.done);
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ret = ctx.err;
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}
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kfree(desc);
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caam_jr_free(jrdev);
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return ret;
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}
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static struct caam_prng_alg caam_prng_alg = {
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.rng = {
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.generate = caam_prng_generate,
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.seed = caam_prng_seed,
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.seedsize = 0,
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.base = {
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.cra_name = "stdrng",
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.cra_driver_name = "prng-caam",
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.cra_priority = 500,
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.cra_ctxsize = sizeof(struct caam_prng_ctx),
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.cra_module = THIS_MODULE,
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.cra_init = caam_prng_init,
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.cra_exit = caam_prng_exit,
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},
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}
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};
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void caam_prng_unregister(void *data)
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{
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if (caam_prng_alg.registered)
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crypto_unregister_rng(&caam_prng_alg.rng);
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}
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int caam_prng_register(struct device *ctrldev)
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{
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struct caam_drv_private *priv = dev_get_drvdata(ctrldev);
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u32 rng_inst;
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int ret = 0;
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/* Check for available RNG blocks before registration */
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if (priv->era < 10)
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rng_inst = (rd_reg32(&priv->jr[0]->perfmon.cha_num_ls) &
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CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
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else
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rng_inst = rd_reg32(&priv->jr[0]->vreg.rng) & CHA_VER_NUM_MASK;
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if (!rng_inst) {
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dev_dbg(ctrldev, "RNG block is not available... skipping registering algorithm\n");
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return ret;
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}
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ret = crypto_register_rng(&caam_prng_alg.rng);
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if (ret) {
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dev_err(ctrldev,
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"couldn't register rng crypto alg: %d\n",
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ret);
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return ret;
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}
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caam_prng_alg.registered = true;
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dev_info(ctrldev,
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"rng crypto API alg registered %s\n", caam_prng_alg.rng.base.cra_driver_name);
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return 0;
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}
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