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3340d739f8
On DRA7, unlike on OMAP4 and OMAP5, the flag mux input numbers used to indicate the source of errors are not continous. Have a way in the driver to catch these and WARN the user of the flag mux input thats either undocumented or wrong. In the similar vein, Timeout errors in AM43x can't be cleared per h/w team, neither does it have a STDERRLOG_MAIN to clear the error. Further, the mux bit offset might not even be indexed into our array of known mux input description, in which case we'd have a abort. So, define a static range check for bit description and any definition which has target_name set to NULL (the ones that are not populated or ones that are specifically marked in the case of discontinous input numbers), can handle the same gracefully. Upon occurance of error from such sources, mask it. Otherwise, we'd have an infinite interrupt source without any means to clear it. NOTE: follow on patch ensures that these masked bits are ignored. [nm@ti.com: rebase, squash and improve] Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Darren Etheridge <detheridge@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com>
153 lines
3.4 KiB
C
153 lines
3.4 KiB
C
/*
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* OMAP L3 Interconnect error handling driver header
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*
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* Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* sricharan <r.sricharan@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __OMAP_L3_NOC_H
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#define __OMAP_L3_NOC_H
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#define L3_MODULES 3
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#define CLEAR_STDERR_LOG (1 << 31)
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#define CUSTOM_ERROR 0x2
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#define STANDARD_ERROR 0x0
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#define INBAND_ERROR 0x0
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#define L3_APPLICATION_ERROR 0x0
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#define L3_DEBUG_ERROR 0x1
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/* L3 TARG register offsets */
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#define L3_TARG_STDERRLOG_MAIN 0x48
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#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
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#define L3_TARG_STDERRLOG_MSTADDR 0x68
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#define L3_FLAGMUX_REGERR0 0xc
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#define L3_FLAGMUX_MASK0 0x8
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#define L3_TARGET_NOT_SUPPORTED NULL
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#define MAX_CLKDM_TARGETS 31
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#define NUM_OF_L3_MASTERS (sizeof(l3_masters)/sizeof(l3_masters[0]))
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/**
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* struct l3_masters_data - L3 Master information
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* @id: ID of the L3 Master
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* @name: master name
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*/
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struct l3_masters_data {
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u32 id;
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char *name;
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};
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/**
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* struct l3_target_data - L3 Target information
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* @offset: Offset from base for L3 Target
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* @name: Target name
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*
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* Target information is organized indexed by bit field definitions.
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*/
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struct l3_target_data {
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u32 offset;
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char *name;
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};
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static u32 l3_flagmux[L3_MODULES] = {
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0x500,
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0x1000,
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0X0200
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};
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static struct l3_target_data l3_target_inst_data_clk1[MAX_CLKDM_TARGETS] = {
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{0x100, "DMM1",},
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{0x200, "DMM2",},
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{0x300, "ABE",},
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{0x400, "L4CFG",},
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{0x600, "CLK2PWRDISC",},
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{0x0, "HOSTCLK1",},
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{0x900, "L4WAKEUP",},
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};
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static struct l3_target_data l3_target_inst_data_clk2[MAX_CLKDM_TARGETS] = {
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{0x500, "CORTEXM3",},
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{0x300, "DSS",},
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{0x100, "GPMC",},
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{0x400, "ISS",},
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{0x700, "IVAHD",},
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{0xD00, "AES1",},
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{0x900, "L4PER0",},
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{0x200, "OCMRAM",},
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{0x100, "GPMCsERROR",},
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{0x600, "SGX",},
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{0x800, "SL2",},
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{0x1600, "C2C",},
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{0x1100, "PWRDISCCLK1",},
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{0xF00, "SHA1",},
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{0xE00, "AES2",},
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{0xC00, "L4PER3",},
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{0xA00, "L4PER1",},
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{0xB00, "L4PER2",},
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{0x0, "HOSTCLK2",},
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{0x1800, "CAL",},
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{0x1700, "LLI",},
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};
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static struct l3_target_data l3_target_inst_data_clk3[MAX_CLKDM_TARGETS] = {
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{0x0100, "EMUSS",},
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{0x0300, "DEBUG SOURCE",},
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{0x0, "HOST CLK3",},
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};
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static struct l3_masters_data l3_masters[] = {
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{ 0x0 , "MPU"},
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{ 0x10, "CS_ADP"},
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{ 0x14, "xxx"},
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{ 0x20, "DSP"},
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{ 0x30, "IVAHD"},
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{ 0x40, "ISS"},
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{ 0x44, "DucatiM3"},
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{ 0x48, "FaceDetect"},
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{ 0x50, "SDMA_Rd"},
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{ 0x54, "SDMA_Wr"},
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{ 0x58, "xxx"},
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{ 0x5C, "xxx"},
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{ 0x60, "SGX"},
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{ 0x70, "DSS"},
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{ 0x80, "C2C"},
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{ 0x88, "xxx"},
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{ 0x8C, "xxx"},
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{ 0x90, "HSI"},
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{ 0xA0, "MMC1"},
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{ 0xA4, "MMC2"},
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{ 0xA8, "MMC6"},
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{ 0xB0, "UNIPRO1"},
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{ 0xC0, "USBHOSTHS"},
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{ 0xC4, "USBOTGHS"},
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{ 0xC8, "USBHOSTFS"}
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};
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static struct l3_target_data *l3_targ[L3_MODULES] = {
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l3_target_inst_data_clk1,
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l3_target_inst_data_clk2,
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l3_target_inst_data_clk3,
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};
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struct omap_l3 {
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struct device *dev;
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/* memory base */
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void __iomem *l3_base[L3_MODULES];
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int debug_irq;
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int app_irq;
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};
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#endif /* __OMAP_L3_NOC_H */
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