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6312d52838
Building an allmodconfig kernel arm64 kernel, the following build error
shows up:
In file included from drivers/crypto/marvell/octeontx2/cn10k_cpt.c:4:
include/linux/soc/marvell/octeontx2/asm.h:38:15: error: unknown type name 'u64'
38 | static inline u64 otx2_atomic64_fetch_add(u64 incr, u64 *ptr)
| ^~~
Include linux/types.h in asm.h so the compiler knows what the type
'u64' are.
Fixes: af3826db74 ("octeontx2-pf: Use hardware register for CQE count")
Signed-off-by: Anders Roxell <anders.roxell@linaro.org>
Link: https://lore.kernel.org/r/20211013135743.3826594-1-anders.roxell@linaro.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
57 lines
1.5 KiB
C
57 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only
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* Copyright (C) 2020 Marvell.
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*/
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#ifndef __SOC_OTX2_ASM_H
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#define __SOC_OTX2_ASM_H
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#include <linux/types.h>
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#if defined(CONFIG_ARM64)
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/*
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* otx2_lmt_flush is used for LMT store operation.
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* On octeontx2 platform CPT instruction enqueue and
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* NIX packet send are only possible via LMTST
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* operations and it uses LDEOR instruction targeting
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* the coprocessor address.
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*/
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#define otx2_lmt_flush(ioaddr) \
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({ \
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u64 result = 0; \
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__asm__ volatile(".cpu generic+lse\n" \
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"ldeor xzr, %x[rf], [%[rs]]" \
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: [rf]"=r" (result) \
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: [rs]"r" (ioaddr)); \
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(result); \
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})
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/*
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* STEORL store to memory with release semantics.
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* This will avoid using DMB barrier after each LMTST
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* operation.
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*/
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#define cn10k_lmt_flush(val, addr) \
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({ \
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__asm__ volatile(".cpu generic+lse\n" \
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"steorl %x[rf],[%[rs]]" \
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: [rf] "+r"(val) \
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: [rs] "r"(addr)); \
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})
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static inline u64 otx2_atomic64_fetch_add(u64 incr, u64 *ptr)
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{
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u64 result;
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asm volatile (".cpu generic+lse\n"
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"ldadda %x[i], %x[r], [%[b]]"
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: [r] "=r" (result), "+m" (*ptr)
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: [i] "r" (incr), [b] "r" (ptr)
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: "memory");
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return result;
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}
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#else
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#define otx2_lmt_flush(ioaddr) ({ 0; })
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#define cn10k_lmt_flush(val, addr) ({ addr = val; })
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#define otx2_atomic64_fetch_add(incr, ptr) ({ incr; })
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#endif
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#endif /* __SOC_OTX2_ASM_H */
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