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![Linus Torvalds](/assets/img/avatar_default.png)
- Core support for soundwire device number allocation - intel driver updates for adding hw_params for DAI ops, hybrid number allocation and power managemnt callback updates - DT header include changes for subsystem -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+vs47OPLdNbVcHzyfBQHDyUjg0cFAmT0vxoACgkQfBQHDyUj g0f/Lg/8CHWdjQzNJVOoJIqY+mFjIKT+QtyRZSpdaQIFYcQF4xcd6v6/rEJzLjgg bMlJ+Icwe19sIq2Yhq69kcecCD5/Arx3tqo2WAwcUF5NykFVQnO/FO+qZYdNM8A9 ohI8+1ZM1qyrC0YocpiUUINOek0MVeLf4wBFFiJMZRVNNMpCH7LrOcs+vH8bLKYn i03dXc/sbM0QyBnfsjnu02wbaq84pFOlbkLJYn21cFoiqryMAXjNXRIpuJ35T5BX iXgHHhVX4vWgOszLM83BhKQnSCemNb4y24ablm9gtVBMpNg2yAyHL0qpAk9nFhGn vVZIup8OVpfziW6O48BBA7HWMBA0fRL8Iz80oH8ZoAAfRl32QGKal37jUaOL7ycO +kMNbJq85v0NDRnUiHeUAY/X5gnnRZpbCLzWxpp3ohx8W0mQctQRFoArhITV7O0Q 38RNfe89Fq6f9poz56tj+d8d/zLx0VzLqPjiuP89HeeOboIjkGtNRfU1z/V9Wh2G 8Fr77rwSAo+wghlFpHE8S9gkyLvMiVeEdNEHskQod7ZvAD2YrfHPLENOW7L0rpGw Eurl+bby1hqgsvA6gQqUQt2xeumeLYelttZYcmMGhPLo7RTYbTckwh6CO2iomNL/ noCtG/mNbR78pOKIab4VWoLcOzFfJ3qCpdOLzYBQYphxJo2oj50= =4w8N -----END PGP SIGNATURE----- Merge tag 'soundwire-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire Pull soundwire updates from Vinod Koul: "Device numbering and intel driver changes are main features: - Core support for soundwire device number allocation - intel driver updates for adding hw_params for DAI ops, hybrid number allocation and power managemnt callback updates - DT header include changes for subsystem" * tag 'soundwire-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire: soundwire: intel_ace2x: add DAI hw_params/prepare/hw_free callbacks soundwire: intel_auxdevice: add hybrid IDA-based device_number allocation soundwire: bus: add callbacks for device_number allocation soundwire: extend parameters of new_peripheral_assigned() callback soundWire: intel_auxdevice: resume 'sdw-master' on startup and system resume soundwire: intel_auxdevice: enable pm_runtime earlier on startup soundwire: Explicitly include correct DT includes
438 lines
15 KiB
C
438 lines
15 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
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/* Copyright(c) 2015-17 Intel Corporation. */
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#ifndef __SDW_INTEL_H
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#define __SDW_INTEL_H
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#include <linux/irqreturn.h>
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#include <linux/soundwire/sdw.h>
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/*********************************************************************
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* cAVS and ACE1.x definitions
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*********************************************************************/
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#define SDW_SHIM_BASE 0x2C000
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#define SDW_ALH_BASE 0x2C800
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#define SDW_SHIM_BASE_ACE 0x38000
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#define SDW_ALH_BASE_ACE 0x24000
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#define SDW_LINK_BASE 0x30000
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#define SDW_LINK_SIZE 0x10000
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/* Intel SHIM Registers Definition */
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/* LCAP */
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#define SDW_SHIM_LCAP 0x0
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#define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0)
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/* LCTL */
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#define SDW_SHIM_LCTL 0x4
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#define SDW_SHIM_LCTL_SPA BIT(0)
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#define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
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#define SDW_SHIM_LCTL_CPA BIT(8)
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#define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
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/* SYNC */
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#define SDW_SHIM_SYNC 0xC
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#define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
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#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
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#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
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#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
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#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
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#define SDW_SHIM_SYNC_CMDSYNC BIT(16)
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#define SDW_SHIM_SYNC_SYNCGO BIT(24)
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/* Control stream capabililities and channel mask */
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#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
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#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
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#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
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#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
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#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
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/* PCM Stream capabilities */
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#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
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#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
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#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
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#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
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/* PCM Stream Channel Map */
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#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
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/* PCM Stream Channel Count */
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#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
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#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
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#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
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#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
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#define SDW_SHIM_PCMSYCM_DIR BIT(15)
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/* IO control */
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#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
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#define SDW_SHIM_IOCTL_MIF BIT(0)
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#define SDW_SHIM_IOCTL_CO BIT(1)
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#define SDW_SHIM_IOCTL_COE BIT(2)
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#define SDW_SHIM_IOCTL_DO BIT(3)
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#define SDW_SHIM_IOCTL_DOE BIT(4)
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#define SDW_SHIM_IOCTL_BKE BIT(5)
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#define SDW_SHIM_IOCTL_WPDD BIT(6)
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#define SDW_SHIM_IOCTL_CIBD BIT(8)
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#define SDW_SHIM_IOCTL_DIBD BIT(9)
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/* Wake Enable*/
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#define SDW_SHIM_WAKEEN 0x190
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#define SDW_SHIM_WAKEEN_ENABLE BIT(0)
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/* Wake Status */
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#define SDW_SHIM_WAKESTS 0x192
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#define SDW_SHIM_WAKESTS_STATUS BIT(0)
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/* AC Timing control */
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#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
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#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
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#define SDW_SHIM_CTMCTL_DODS BIT(1)
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#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
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/* Intel ALH Register definitions */
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#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
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#define SDW_ALH_NUM_STREAMS 64
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#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
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#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
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#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
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/*********************************************************************
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* ACE2.x definitions for SHIM registers - only accessible when the
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* HDAudio extended link LCTL.SPA/CPA = 1.
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*********************************************************************/
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/* x variable is link index */
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#define SDW_SHIM2_GENERIC_BASE(x) (0x00030000 + 0x8000 * (x))
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#define SDW_IP_BASE(x) (0x00030100 + 0x8000 * (x))
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#define SDW_SHIM2_VS_BASE(x) (0x00036000 + 0x8000 * (x))
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/* SHIM2 Generic Registers */
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/* Read-only capabilities */
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#define SDW_SHIM2_LECAP 0x00
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#define SDW_SHIM2_LECAP_HDS BIT(0) /* unset -> Host mode */
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#define SDW_SHIM2_LECAP_MLC GENMASK(3, 1) /* Number of Lanes */
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/* PCM Stream capabilities */
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#define SDW_SHIM2_PCMSCAP 0x10
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#define SDW_SHIM2_PCMSCAP_ISS GENMASK(3, 0) /* Input-only streams */
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#define SDW_SHIM2_PCMSCAP_OSS GENMASK(7, 4) /* Output-only streams */
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#define SDW_SHIM2_PCMSCAP_BSS GENMASK(12, 8) /* Bidirectional streams */
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/* Read-only PCM Stream Channel Count, y variable is stream */
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#define SDW_SHIM2_PCMSYCHC(y) (0x14 + (0x4 * (y)))
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#define SDW_SHIM2_PCMSYCHC_CS GENMASK(3, 0) /* Channels Supported */
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/* PCM Stream Channel Map */
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#define SDW_SHIM2_PCMSYCHM(y) (0x16 + (0x4 * (y)))
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#define SDW_SHIM2_PCMSYCHM_LCHAN GENMASK(3, 0) /* Lowest channel used by the FIFO port */
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#define SDW_SHIM2_PCMSYCHM_HCHAN GENMASK(7, 4) /* Lowest channel used by the FIFO port */
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#define SDW_SHIM2_PCMSYCHM_STRM GENMASK(13, 8) /* HDaudio stream tag */
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#define SDW_SHIM2_PCMSYCHM_DIR BIT(15) /* HDaudio stream direction */
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/* SHIM2 vendor-specific registers */
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#define SDW_SHIM2_INTEL_VS_LVSCTL 0x04
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#define SDW_SHIM2_INTEL_VS_LVSCTL_FCG BIT(26)
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#define SDW_SHIM2_INTEL_VS_LVSCTL_MLCS GENMASK(29, 27)
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#define SDW_SHIM2_INTEL_VS_LVSCTL_DCGD BIT(30)
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#define SDW_SHIM2_INTEL_VS_LVSCTL_ICGD BIT(31)
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#define SDW_SHIM2_MLCS_XTAL_CLK 0x0
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#define SDW_SHIM2_MLCS_CARDINAL_CLK 0x1
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#define SDW_SHIM2_MLCS_AUDIO_PLL_CLK 0x2
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#define SDW_SHIM2_MLCS_MCLK_INPUT_CLK 0x3
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#define SDW_SHIM2_MLCS_WOV_RING_OSC_CLK 0x4
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#define SDW_SHIM2_INTEL_VS_WAKEEN 0x08
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#define SDW_SHIM2_INTEL_VS_WAKEEN_PWE BIT(0)
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#define SDW_SHIM2_INTEL_VS_WAKESTS 0x0A
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#define SDW_SHIM2_INTEL_VS_WAKEEN_PWS BIT(0)
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#define SDW_SHIM2_INTEL_VS_IOCTL 0x0C
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#define SDW_SHIM2_INTEL_VS_IOCTL_MIF BIT(0)
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#define SDW_SHIM2_INTEL_VS_IOCTL_CO BIT(1)
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#define SDW_SHIM2_INTEL_VS_IOCTL_COE BIT(2)
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#define SDW_SHIM2_INTEL_VS_IOCTL_DO BIT(3)
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#define SDW_SHIM2_INTEL_VS_IOCTL_DOE BIT(4)
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#define SDW_SHIM2_INTEL_VS_IOCTL_BKE BIT(5)
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#define SDW_SHIM2_INTEL_VS_IOCTL_WPDD BIT(6)
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#define SDW_SHIM2_INTEL_VS_IOCTL_ODC BIT(7)
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#define SDW_SHIM2_INTEL_VS_IOCTL_CIBD BIT(8)
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#define SDW_SHIM2_INTEL_VS_IOCTL_DIBD BIT(9)
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#define SDW_SHIM2_INTEL_VS_IOCTL_HAMIFD BIT(10)
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#define SDW_SHIM2_INTEL_VS_ACTMCTL 0x0E
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#define SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE BIT(0)
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#define SDW_SHIM2_INTEL_VS_ACTMCTL_DODS BIT(1)
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#define SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE BIT(2)
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#define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS GENMASK(4, 3)
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#define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE BIT(5)
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/**
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* struct sdw_intel_stream_params_data: configuration passed during
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* the @params_stream callback, e.g. for interaction with DSP
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* firmware.
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*/
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struct sdw_intel_stream_params_data {
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struct snd_pcm_substream *substream;
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struct snd_soc_dai *dai;
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struct snd_pcm_hw_params *hw_params;
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int link_id;
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int alh_stream_id;
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};
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/**
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* struct sdw_intel_stream_free_data: configuration passed during
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* the @free_stream callback, e.g. for interaction with DSP
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* firmware.
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*/
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struct sdw_intel_stream_free_data {
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struct snd_pcm_substream *substream;
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struct snd_soc_dai *dai;
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int link_id;
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};
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/**
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* struct sdw_intel_ops: Intel audio driver callback ops
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*
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*/
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struct sdw_intel_ops {
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int (*params_stream)(struct device *dev,
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struct sdw_intel_stream_params_data *params_data);
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int (*free_stream)(struct device *dev,
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struct sdw_intel_stream_free_data *free_data);
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int (*trigger)(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai);
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};
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/**
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* struct sdw_intel_acpi_info - Soundwire Intel information found in ACPI tables
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* @handle: ACPI controller handle
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* @count: link count found with "sdw-master-count" property
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* @link_mask: bit-wise mask listing links enabled by BIOS menu
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*
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* this structure could be expanded to e.g. provide all the _ADR
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* information in case the link_mask is not sufficient to identify
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* platform capabilities.
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*/
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struct sdw_intel_acpi_info {
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acpi_handle handle;
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int count;
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u32 link_mask;
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};
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struct sdw_intel_link_dev;
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/* Intel clock-stop/pm_runtime quirk definitions */
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/*
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* Force the clock to remain on during pm_runtime suspend. This might
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* be needed if Slave devices do not have an alternate clock source or
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* if the latency requirements are very strict.
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*/
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#define SDW_INTEL_CLK_STOP_NOT_ALLOWED BIT(0)
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/*
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* Stop the bus during pm_runtime suspend. If set, a complete bus
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* reset and re-enumeration will be performed when the bus
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* restarts. This mode shall not be used if Slave devices can generate
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* in-band wakes.
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*/
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#define SDW_INTEL_CLK_STOP_TEARDOWN BIT(1)
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/*
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* Stop the bus during pm_suspend if Slaves are not wake capable
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* (e.g. speaker amplifiers). The clock-stop mode is typically
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* slightly higher power than when the IP is completely powered-off.
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*/
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#define SDW_INTEL_CLK_STOP_WAKE_CAPABLE_ONLY BIT(2)
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/*
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* Require a bus reset (and complete re-enumeration) when exiting
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* clock stop modes. This may be needed if the controller power was
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* turned off and all context lost. This quirk shall not be used if a
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* Slave device needs to remain enumerated and keep its context,
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* e.g. to provide the reasons for the wake, report acoustic events or
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* pass a history buffer.
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*/
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#define SDW_INTEL_CLK_STOP_BUS_RESET BIT(3)
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struct hdac_bus;
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/**
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* struct sdw_intel_ctx - context allocated by the controller
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* driver probe
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* @count: link count
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* @mmio_base: mmio base of SoundWire registers, only used to check
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* hardware capabilities after all power dependencies are settled.
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* @link_mask: bit-wise mask listing SoundWire links reported by the
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* Controller
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* @num_slaves: total number of devices exposed across all enabled links
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* @handle: ACPI parent handle
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* @ldev: information for each link (controller-specific and kept
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* opaque here)
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* @ids: array of slave_id, representing Slaves exposed across all enabled
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* links
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* @link_list: list to handle interrupts across all links
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* @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.
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* @shim_mask: flags to track initialization of SHIM shared registers
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* @shim_base: sdw shim base.
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* @alh_base: sdw alh base.
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*/
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struct sdw_intel_ctx {
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int count;
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void __iomem *mmio_base;
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u32 link_mask;
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int num_slaves;
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acpi_handle handle;
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struct sdw_intel_link_dev **ldev;
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struct sdw_extended_slave_id *ids;
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struct list_head link_list;
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struct mutex shim_lock; /* lock for access to shared SHIM registers */
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u32 shim_mask;
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u32 shim_base;
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u32 alh_base;
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};
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/**
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* struct sdw_intel_res - Soundwire Intel global resource structure,
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* typically populated by the DSP driver
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*
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* @hw_ops: abstraction for platform ops
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* @count: link count
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* @mmio_base: mmio base of SoundWire registers
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* @irq: interrupt number
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* @handle: ACPI parent handle
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* @parent: parent device
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* @ops: callback ops
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* @dev: device implementing hwparams and free callbacks
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* @link_mask: bit-wise mask listing links selected by the DSP driver
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* This mask may be a subset of the one reported by the controller since
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* machine-specific quirks are handled in the DSP driver.
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* @clock_stop_quirks: mask array of possible behaviors requested by the
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* DSP driver. The quirks are common for all links for now.
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* @shim_base: sdw shim base.
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* @alh_base: sdw alh base.
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* @ext: extended HDaudio link support
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* @hbus: hdac_bus pointer, needed for power management
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* @eml_lock: mutex protecting shared registers in the HDaudio multi-link
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* space
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*/
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struct sdw_intel_res {
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const struct sdw_intel_hw_ops *hw_ops;
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int count;
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void __iomem *mmio_base;
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int irq;
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acpi_handle handle;
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struct device *parent;
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const struct sdw_intel_ops *ops;
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struct device *dev;
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u32 link_mask;
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u32 clock_stop_quirks;
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u32 shim_base;
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u32 alh_base;
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bool ext;
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struct hdac_bus *hbus;
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struct mutex *eml_lock;
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};
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/*
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* On Intel platforms, the SoundWire IP has dependencies on power
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* rails shared with the DSP, and the initialization steps are split
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* in three. First an ACPI scan to check what the firmware describes
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* in DSDT tables, then an allocation step (with no hardware
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* configuration but with all the relevant devices created) and last
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* the actual hardware configuration. The final stage is a global
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* interrupt enable which is controlled by the DSP driver. Splitting
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* these phases helps simplify the boot flow and make early decisions
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* on e.g. which machine driver to select (I2S mode, HDaudio or
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* SoundWire).
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*/
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int sdw_intel_acpi_scan(acpi_handle *parent_handle,
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struct sdw_intel_acpi_info *info);
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void sdw_intel_process_wakeen_event(struct sdw_intel_ctx *ctx);
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struct sdw_intel_ctx *
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sdw_intel_probe(struct sdw_intel_res *res);
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int sdw_intel_startup(struct sdw_intel_ctx *ctx);
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void sdw_intel_exit(struct sdw_intel_ctx *ctx);
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irqreturn_t sdw_intel_thread(int irq, void *dev_id);
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#define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1)
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struct sdw_intel;
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/* struct intel_sdw_hw_ops - SoundWire ops for Intel platforms.
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* @debugfs_init: initialize all debugfs capabilities
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* @debugfs_exit: close and cleanup debugfs capabilities
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* @register_dai: read all PDI information and register DAIs
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* @check_clock_stop: throw error message if clock is not stopped.
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* @start_bus: normal start
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* @start_bus_after_reset: start after reset
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* @start_bus_after_clock_stop: start after mode0 clock stop
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* @stop_bus: stop all bus
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* @link_power_up: power-up using chip-specific helpers
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* @link_power_down: power-down with chip-specific helpers
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* @shim_check_wake: check if a wake was received
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* @shim_wake: enable/disable in-band wake management
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* @pre_bank_switch: helper for bus management
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* @post_bank_switch: helper for bus management
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* @sync_arm: helper for multi-link synchronization
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* @sync_go_unlocked: helper for multi-link synchronization -
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* shim_lock is assumed to be locked at higher level
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* @sync_go: helper for multi-link synchronization
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* @sync_check_cmdsync_unlocked: helper for multi-link synchronization
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* and bank switch - shim_lock is assumed to be locked at higher level
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* @program_sdi: helper for codec command/control based on dev_num
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*/
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struct sdw_intel_hw_ops {
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void (*debugfs_init)(struct sdw_intel *sdw);
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void (*debugfs_exit)(struct sdw_intel *sdw);
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int (*register_dai)(struct sdw_intel *sdw);
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void (*check_clock_stop)(struct sdw_intel *sdw);
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int (*start_bus)(struct sdw_intel *sdw);
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int (*start_bus_after_reset)(struct sdw_intel *sdw);
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int (*start_bus_after_clock_stop)(struct sdw_intel *sdw);
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int (*stop_bus)(struct sdw_intel *sdw, bool clock_stop);
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int (*link_power_up)(struct sdw_intel *sdw);
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int (*link_power_down)(struct sdw_intel *sdw);
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int (*shim_check_wake)(struct sdw_intel *sdw);
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void (*shim_wake)(struct sdw_intel *sdw, bool wake_enable);
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int (*pre_bank_switch)(struct sdw_intel *sdw);
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int (*post_bank_switch)(struct sdw_intel *sdw);
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void (*sync_arm)(struct sdw_intel *sdw);
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int (*sync_go_unlocked)(struct sdw_intel *sdw);
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int (*sync_go)(struct sdw_intel *sdw);
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bool (*sync_check_cmdsync_unlocked)(struct sdw_intel *sdw);
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void (*program_sdi)(struct sdw_intel *sdw, int dev_num);
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};
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extern const struct sdw_intel_hw_ops sdw_intel_cnl_hw_ops;
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extern const struct sdw_intel_hw_ops sdw_intel_lnl_hw_ops;
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/*
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* IDA min selected to allow for 5 unconstrained devices per link,
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* and 6 system-unique Device Numbers for wake-capable devices.
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*/
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#define SDW_INTEL_DEV_NUM_IDA_MIN 6
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#endif
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