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fe96df93f8
The Allwinner SoCs have a AHCI controllers that is supported in Linux, with a matching Device Tree binding. Now that we have the DT validation in place, let's convert the device tree bindings for that controller over to a YAML schemas. Signed-off-by: Maxime Ripard <maxime@cerno.tech> [robh: 'maxItems: 1' for resets] Signed-off-by: Rob Herring <robh@kernel.org>
67 lines
1.3 KiB
YAML
67 lines
1.3 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ata/allwinner,sun8i-r40-ahci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner R40 AHCI SATA Controller bindings
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <mripard@kernel.org>
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properties:
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compatible:
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const: allwinner,sun8i-r40-ahci
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reg:
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maxItems: 1
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clocks:
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items:
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- description: AHCI Bus Clock
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- description: AHCI Module Clock
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interrupts:
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maxItems: 1
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resets:
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maxItems: 1
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reset-names:
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const: ahci
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ahci-supply:
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description: Regulator for the AHCI controller
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phy-supply:
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description: Regulator for the SATA PHY power
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required:
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- compatible
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- reg
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- clocks
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- interrupts
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- resets
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- reset-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun8i-r40-ccu.h>
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#include <dt-bindings/reset/sun8i-r40-ccu.h>
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ahci: sata@1c18000 {
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compatible = "allwinner,sun8i-r40-ahci";
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reg = <0x01c18000 0x1000>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
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resets = <&ccu RST_BUS_SATA>;
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reset-names = "ahci";
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ahci-supply = <®_dldo4>;
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phy-supply = <®_eldo3>;
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};
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...
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