Linus Walleij 094b10cb79 dt-bindings: gnss: Add two more chips ... The CSR GSD4t is a CSR product using the SiRFstarIV core, and the CSR CSRG05TA03-ICJE-R is a CSR product using the SiRFstarV core. These chips have a SRESETN line that can be pulled low to hard reset the chip and in some designs this is connected to a GPIO, so add this as an optional property. Update the example with a reset line so users see that it need to be tagged as active low. Cc: devicetree@vger.kernel.org Cc: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220317225844.1262643-4-linus.walleij@linaro.org		2022-03-20 15:02:22 -04:00
..
gnss-common.yaml	dt-bindings: gnss: Rewrite common bindings in YAML	2022-03-20 14:53:50 -04:00
mediatek.txt	dt-bindings: gnss: add mediatek binding	2019-02-15 16:53:57 +01:00
sirfstar.yaml	dt-bindings: gnss: Add two more chips	2022-03-20 15:02:22 -04:00
u-blox,neo-6m.yaml	dt-bindings: gnss: Modify u-blox to use common bindings	2022-03-20 14:54:56 -04:00