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f28b24042b
Update PCI endpoint binding document for UniPhier NX1 SoC. Add a compatible string, clock and reset lines for the SoC to the document. Link: https://lore.kernel.org/r/1644480596-20037-2-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
108 lines
2.3 KiB
YAML
108 lines
2.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Socionext UniPhier PCIe endpoint controller
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description: |
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UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
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PCI core. It shares common features with the PCIe DesignWare core and
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inherits common properties defined in
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Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
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maintainers:
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- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
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properties:
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compatible:
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enum:
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- socionext,uniphier-pro5-pcie-ep
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- socionext,uniphier-nx1-pcie-ep
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reg:
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minItems: 4
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maxItems: 5
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reg-names:
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oneOf:
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- items:
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- const: dbi
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- const: dbi2
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- const: link
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- const: addr_space
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- items:
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- const: dbi
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- const: dbi2
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- const: link
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- const: addr_space
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- const: atu
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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oneOf:
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- items: # for Pro5
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- const: gio
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- const: link
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- const: link # for NX1
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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oneOf:
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- items: # for Pro5
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- const: gio
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- const: link
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- const: link # for NX1
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num-ib-windows:
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const: 16
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num-ob-windows:
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const: 16
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num-lanes: true
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phys:
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maxItems: 1
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phy-names:
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const: pcie-phy
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- resets
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- reset-names
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unevaluatedProperties: false
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examples:
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- |
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pcie_ep: pcie-ep@66000000 {
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compatible = "socionext,uniphier-pro5-pcie-ep";
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reg-names = "dbi", "dbi2", "link", "addr_space";
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reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
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<0x66010000 0x10000>, <0x67000000 0x400000>;
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clock-names = "gio", "link";
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clocks = <&sys_clk 12>, <&sys_clk 24>;
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reset-names = "gio", "link";
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resets = <&sys_rst 12>, <&sys_rst 24>;
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num-ib-windows = <16>;
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num-ob-windows = <16>;
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num-lanes = <4>;
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phy-names = "pcie-phy";
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phys = <&pcie_phy>;
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};
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