mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-11-01 00:48:50 +00:00
fcda50c8f4
Global symbols in the kernel should be prefixed by the name of the subsystem and/or driver to avoid conflicts when all code is built-in. In this case, function names like 'hdmi_register' or 'hdmi_set_mode' are way too generic for an MSM specific DRM driver, so I'm renaming them all to msm_hdmi_* here. I also rename a lot of the 'static' symbols along with the global names for consistency, even though those are relatively harmless; they might only be slightly confusing when they show up in backtraces. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Rob Clark <robdclark@gmail.com>
138 lines
4.7 KiB
C
138 lines
4.7 KiB
C
/*
|
|
* Copyright (C) 2013 Red Hat
|
|
* Author: Rob Clark <robdclark@gmail.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License version 2 as published by
|
|
* the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope that it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License along with
|
|
* this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#include "hdmi.h"
|
|
|
|
static void hdmi_phy_8x60_powerup(struct hdmi_phy *phy,
|
|
unsigned long int pixclock)
|
|
{
|
|
/* De-serializer delay D/C for non-lbk mode: */
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG0,
|
|
HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(3));
|
|
|
|
if (pixclock == 27000000) {
|
|
/* video_format == HDMI_VFRMT_720x480p60_16_9 */
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG1,
|
|
HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) |
|
|
HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(3));
|
|
} else {
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG1,
|
|
HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) |
|
|
HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(4));
|
|
}
|
|
|
|
/* No matter what, start from the power down mode: */
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
|
|
HDMI_8x60_PHY_REG2_PD_PWRGEN |
|
|
HDMI_8x60_PHY_REG2_PD_PLL |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
|
|
HDMI_8x60_PHY_REG2_PD_DESER);
|
|
|
|
/* Turn PowerGen on: */
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
|
|
HDMI_8x60_PHY_REG2_PD_PLL |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
|
|
HDMI_8x60_PHY_REG2_PD_DESER);
|
|
|
|
/* Turn PLL power on: */
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
|
|
HDMI_8x60_PHY_REG2_PD_DESER);
|
|
|
|
/* Write to HIGH after PLL power down de-assert: */
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG3,
|
|
HDMI_8x60_PHY_REG3_PLL_ENABLE);
|
|
|
|
/* ASIC power on; PHY REG9 = 0 */
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG9, 0);
|
|
|
|
/* Enable PLL lock detect, PLL lock det will go high after lock
|
|
* Enable the re-time logic
|
|
*/
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG12,
|
|
HDMI_8x60_PHY_REG12_RETIMING_EN |
|
|
HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN);
|
|
|
|
/* Drivers are on: */
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
|
|
HDMI_8x60_PHY_REG2_PD_DESER);
|
|
|
|
/* If the RX detector is needed: */
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
|
|
HDMI_8x60_PHY_REG2_RCV_SENSE_EN |
|
|
HDMI_8x60_PHY_REG2_PD_DESER);
|
|
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG4, 0);
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG5, 0);
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG6, 0);
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG7, 0);
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG8, 0);
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG9, 0);
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG10, 0);
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG11, 0);
|
|
|
|
/* If we want to use lock enable based on counting: */
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG12,
|
|
HDMI_8x60_PHY_REG12_RETIMING_EN |
|
|
HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN |
|
|
HDMI_8x60_PHY_REG12_FORCE_LOCK);
|
|
}
|
|
|
|
static void hdmi_phy_8x60_powerdown(struct hdmi_phy *phy)
|
|
{
|
|
/* Assert RESET PHY from controller */
|
|
hdmi_phy_write(phy, REG_HDMI_PHY_CTRL,
|
|
HDMI_PHY_CTRL_SW_RESET);
|
|
udelay(10);
|
|
/* De-assert RESET PHY from controller */
|
|
hdmi_phy_write(phy, REG_HDMI_PHY_CTRL, 0);
|
|
/* Turn off Driver */
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
|
|
HDMI_8x60_PHY_REG2_PD_DESER);
|
|
udelay(10);
|
|
/* Disable PLL */
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG3, 0);
|
|
/* Power down PHY, but keep RX-sense: */
|
|
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
|
|
HDMI_8x60_PHY_REG2_RCV_SENSE_EN |
|
|
HDMI_8x60_PHY_REG2_PD_PWRGEN |
|
|
HDMI_8x60_PHY_REG2_PD_PLL |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
|
|
HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
|
|
HDMI_8x60_PHY_REG2_PD_DESER);
|
|
}
|
|
|
|
const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg = {
|
|
.type = MSM_HDMI_PHY_8x60,
|
|
.powerup = hdmi_phy_8x60_powerup,
|
|
.powerdown = hdmi_phy_8x60_powerdown,
|
|
};
|