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Add a clock driver for the cpu dynamic divider, this divider needs to have a flag set before setting the divider value then removed while writing the new value to the register. This drivers implements this behavior and will be used essentially on the Amlogic G12A and G12B SoCs for cpu clock trees. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
21 lines
895 B
Makefile
21 lines
895 B
Makefile
# SPDX-License-Identifier: GPL-2.0-only
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# Amlogic clock drivers
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obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
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obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
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obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
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obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o
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obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
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obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o
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obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
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obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o
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obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
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obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
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# Amlogic Clock controllers
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obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
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obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
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obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
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obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
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obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
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