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9b8e1a5e46
This patch adds all necessary header files and Kbuild plumbing for the core driver for Silicon Laboratories Si476x series of AM/FM tuner chips. The driver as a whole is implemented as an MFD device and this patch adds a core portion of it that provides all the necessary functionality to the two other drivers that represent radio and audio codec subsystems of the chip. Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
267 lines
6.4 KiB
C
267 lines
6.4 KiB
C
/*
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* include/media/si476x-platform.h -- Platform data specific definitions
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*
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* Copyright (C) 2013 Andrey Smirnov
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*
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* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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*/
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#ifndef __SI476X_PLATFORM_H__
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#define __SI476X_PLATFORM_H__
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/* It is possible to select one of the four adresses using pins A0
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* and A1 on SI476x */
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#define SI476X_I2C_ADDR_1 0x60
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#define SI476X_I2C_ADDR_2 0x61
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#define SI476X_I2C_ADDR_3 0x62
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#define SI476X_I2C_ADDR_4 0x63
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enum si476x_iqclk_config {
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SI476X_IQCLK_NOOP = 0,
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SI476X_IQCLK_TRISTATE = 1,
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SI476X_IQCLK_IQ = 21,
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};
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enum si476x_iqfs_config {
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SI476X_IQFS_NOOP = 0,
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SI476X_IQFS_TRISTATE = 1,
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SI476X_IQFS_IQ = 21,
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};
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enum si476x_iout_config {
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SI476X_IOUT_NOOP = 0,
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SI476X_IOUT_TRISTATE = 1,
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SI476X_IOUT_OUTPUT = 22,
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};
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enum si476x_qout_config {
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SI476X_QOUT_NOOP = 0,
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SI476X_QOUT_TRISTATE = 1,
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SI476X_QOUT_OUTPUT = 22,
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};
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enum si476x_dclk_config {
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SI476X_DCLK_NOOP = 0,
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SI476X_DCLK_TRISTATE = 1,
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SI476X_DCLK_DAUDIO = 10,
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};
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enum si476x_dfs_config {
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SI476X_DFS_NOOP = 0,
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SI476X_DFS_TRISTATE = 1,
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SI476X_DFS_DAUDIO = 10,
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};
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enum si476x_dout_config {
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SI476X_DOUT_NOOP = 0,
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SI476X_DOUT_TRISTATE = 1,
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SI476X_DOUT_I2S_OUTPUT = 12,
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SI476X_DOUT_I2S_INPUT = 13,
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};
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enum si476x_xout_config {
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SI476X_XOUT_NOOP = 0,
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SI476X_XOUT_TRISTATE = 1,
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SI476X_XOUT_I2S_INPUT = 13,
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SI476X_XOUT_MODE_SELECT = 23,
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};
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enum si476x_icin_config {
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SI476X_ICIN_NOOP = 0,
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SI476X_ICIN_TRISTATE = 1,
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SI476X_ICIN_GPO1_HIGH = 2,
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SI476X_ICIN_GPO1_LOW = 3,
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SI476X_ICIN_IC_LINK = 30,
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};
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enum si476x_icip_config {
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SI476X_ICIP_NOOP = 0,
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SI476X_ICIP_TRISTATE = 1,
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SI476X_ICIP_GPO2_HIGH = 2,
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SI476X_ICIP_GPO2_LOW = 3,
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SI476X_ICIP_IC_LINK = 30,
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};
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enum si476x_icon_config {
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SI476X_ICON_NOOP = 0,
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SI476X_ICON_TRISTATE = 1,
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SI476X_ICON_I2S = 10,
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SI476X_ICON_IC_LINK = 30,
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};
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enum si476x_icop_config {
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SI476X_ICOP_NOOP = 0,
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SI476X_ICOP_TRISTATE = 1,
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SI476X_ICOP_I2S = 10,
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SI476X_ICOP_IC_LINK = 30,
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};
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enum si476x_lrout_config {
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SI476X_LROUT_NOOP = 0,
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SI476X_LROUT_TRISTATE = 1,
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SI476X_LROUT_AUDIO = 2,
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SI476X_LROUT_MPX = 3,
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};
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enum si476x_intb_config {
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SI476X_INTB_NOOP = 0,
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SI476X_INTB_TRISTATE = 1,
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SI476X_INTB_DAUDIO = 10,
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SI476X_INTB_IRQ = 40,
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};
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enum si476x_a1_config {
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SI476X_A1_NOOP = 0,
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SI476X_A1_TRISTATE = 1,
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SI476X_A1_IRQ = 40,
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};
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struct si476x_pinmux {
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enum si476x_dclk_config dclk;
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enum si476x_dfs_config dfs;
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enum si476x_dout_config dout;
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enum si476x_xout_config xout;
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enum si476x_iqclk_config iqclk;
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enum si476x_iqfs_config iqfs;
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enum si476x_iout_config iout;
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enum si476x_qout_config qout;
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enum si476x_icin_config icin;
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enum si476x_icip_config icip;
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enum si476x_icon_config icon;
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enum si476x_icop_config icop;
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enum si476x_lrout_config lrout;
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enum si476x_intb_config intb;
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enum si476x_a1_config a1;
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};
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enum si476x_ibias6x {
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SI476X_IBIAS6X_OTHER = 0,
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SI476X_IBIAS6X_RCVR1_NON_4MHZ_CLK = 1,
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};
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enum si476x_xstart {
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SI476X_XSTART_MULTIPLE_TUNER = 0x11,
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SI476X_XSTART_NORMAL = 0x77,
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};
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enum si476x_freq {
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SI476X_FREQ_4_MHZ = 0,
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SI476X_FREQ_37P209375_MHZ = 1,
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SI476X_FREQ_36P4_MHZ = 2,
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SI476X_FREQ_37P8_MHZ = 3,
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};
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enum si476x_xmode {
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SI476X_XMODE_CRYSTAL_RCVR1 = 1,
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SI476X_XMODE_EXT_CLOCK = 2,
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SI476X_XMODE_CRYSTAL_RCVR2_3 = 3,
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};
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enum si476x_xbiashc {
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SI476X_XBIASHC_SINGLE_RECEIVER = 0,
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SI476X_XBIASHC_MULTIPLE_RECEIVER = 1,
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};
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enum si476x_xbias {
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SI476X_XBIAS_RCVR2_3 = 0,
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SI476X_XBIAS_4MHZ_RCVR1 = 3,
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SI476X_XBIAS_RCVR1 = 7,
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};
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enum si476x_func {
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SI476X_FUNC_BOOTLOADER = 0,
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SI476X_FUNC_FM_RECEIVER = 1,
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SI476X_FUNC_AM_RECEIVER = 2,
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SI476X_FUNC_WB_RECEIVER = 3,
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};
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/**
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* @xcload: Selects the amount of additional on-chip capacitance to
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* be connected between XTAL1 and gnd and between XTAL2 and
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* GND. One half of the capacitance value shown here is the
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* additional load capacitance presented to the xtal. The
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* minimum step size is 0.277 pF. Recommended value is 0x28
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* but it will be layout dependent. Range is 0–0x3F i.e.
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* (0–16.33 pF)
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* @ctsien: enable CTSINT(interrupt request when CTS condition
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* arises) when set
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* @intsel: when set A1 pin becomes the interrupt pin; otherwise,
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* INTB is the interrupt pin
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* @func: selects the boot function of the device. I.e.
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* SI476X_BOOTLOADER - Boot loader
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* SI476X_FM_RECEIVER - FM receiver
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* SI476X_AM_RECEIVER - AM receiver
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* SI476X_WB_RECEIVER - Weatherband receiver
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* @freq: oscillator's crystal frequency:
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* SI476X_XTAL_37P209375_MHZ - 37.209375 Mhz
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* SI476X_XTAL_36P4_MHZ - 36.4 Mhz
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* SI476X_XTAL_37P8_MHZ - 37.8 Mhz
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*/
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struct si476x_power_up_args {
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enum si476x_ibias6x ibias6x;
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enum si476x_xstart xstart;
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u8 xcload;
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bool fastboot;
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enum si476x_xbiashc xbiashc;
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enum si476x_xbias xbias;
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enum si476x_func func;
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enum si476x_freq freq;
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enum si476x_xmode xmode;
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};
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/**
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* enum si476x_phase_diversity_mode - possbile phase diversity modes
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* for SI4764/5/6/7 chips.
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*
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* @SI476X_PHDIV_DISABLED: Phase diversity feature is
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* disabled.
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* @SI476X_PHDIV_PRIMARY_COMBINING: Tuner works as a primary tuner
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* in combination with a
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* secondary one.
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* @SI476X_PHDIV_PRIMARY_ANTENNA: Tuner works as a primary tuner
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* using only its own antenna.
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* @SI476X_PHDIV_SECONDARY_ANTENNA: Tuner works as a primary tuner
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* usning seconary tuner's antenna.
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* @SI476X_PHDIV_SECONDARY_COMBINING: Tuner works as a secondary
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* tuner in combination with the
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* primary one.
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*/
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enum si476x_phase_diversity_mode {
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SI476X_PHDIV_DISABLED = 0,
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SI476X_PHDIV_PRIMARY_COMBINING = 1,
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SI476X_PHDIV_PRIMARY_ANTENNA = 2,
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SI476X_PHDIV_SECONDARY_ANTENNA = 3,
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SI476X_PHDIV_SECONDARY_COMBINING = 5,
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};
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/*
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* Platform dependent definition
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*/
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struct si476x_platform_data {
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int gpio_reset; /* < 0 if not used */
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struct si476x_power_up_args power_up_parameters;
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enum si476x_phase_diversity_mode diversity_mode;
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struct si476x_pinmux pinmux;
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};
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#endif /* __SI476X_PLATFORM_H__ */
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