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a0fbb35ecd
Push responsibility for managing the clock during DPMS down into the variant backend, rather than the CRTC layer having knowledge of its state. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
105 lines
2.5 KiB
C
105 lines
2.5 KiB
C
/*
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* Copyright (C) 2012 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Armada 510 (aka Dove) variant support
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <drm/drm_crtc_helper.h>
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#include "armada_crtc.h"
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#include "armada_drm.h"
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#include "armada_hw.h"
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static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev)
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{
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struct clk *clk;
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clk = devm_clk_get(dev, "ext_ref_clk1");
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if (IS_ERR(clk))
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return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER : PTR_ERR(clk);
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dcrtc->extclk[0] = clk;
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/* Lower the watermark so to eliminate jitter at higher bandwidths */
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armada_updatel(0x20, (1 << 11) | 0xff, dcrtc->base + LCD_CFG_RDREG4F);
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/* Initialise SPU register */
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writel_relaxed(ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,
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dcrtc->base + LCD_SPU_ADV_REG);
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return 0;
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}
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/*
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* Armada510 specific SCLK register selection.
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* This gets called with sclk = NULL to test whether the mode is
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* supportable, and again with sclk != NULL to set the clocks up for
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* that. The former can return an error, but the latter is expected
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* not to.
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*
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* We currently are pretty rudimentary here, always selecting
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* EXT_REF_CLK_1 for LCD0 and erroring LCD1. This needs improvement!
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*/
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static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc,
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const struct drm_display_mode *mode, uint32_t *sclk)
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{
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struct clk *clk = dcrtc->extclk[0];
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int ret;
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if (dcrtc->num == 1)
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return -EINVAL;
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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if (dcrtc->clk != clk) {
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ret = clk_prepare_enable(clk);
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if (ret)
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return ret;
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dcrtc->clk = clk;
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}
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if (sclk) {
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uint32_t rate, ref, div;
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rate = mode->clock * 1000;
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ref = clk_round_rate(clk, rate);
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div = DIV_ROUND_UP(ref, rate);
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if (div < 1)
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div = 1;
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clk_set_rate(clk, ref);
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*sclk = div | SCLK_510_EXTCLK1;
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}
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return 0;
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}
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static void armada510_crtc_disable(struct armada_crtc *dcrtc)
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{
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if (!IS_ERR(dcrtc->clk)) {
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clk_disable_unprepare(dcrtc->clk);
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dcrtc->clk = ERR_PTR(-EINVAL);
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}
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}
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static void armada510_crtc_enable(struct armada_crtc *dcrtc,
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const struct drm_display_mode *mode)
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{
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if (IS_ERR(dcrtc->clk)) {
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dcrtc->clk = dcrtc->extclk[0];
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WARN_ON(clk_prepare_enable(dcrtc->clk));
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}
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}
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const struct armada_variant armada510_ops = {
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.has_spu_adv_reg = true,
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.init = armada510_crtc_init,
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.compute_clock = armada510_crtc_compute_clock,
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.disable = armada510_crtc_disable,
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.enable = armada510_crtc_enable,
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};
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