Heinrich Schuchardt 34fc9cc3ae riscv: dts: microchip: correct L2 cache interrupts ... The "PolarFire SoC MSS Technical Reference Manual" documents the following PLIC interrupts: 1 - L2 Cache Controller Signals when a metadata correction event occurs 2 - L2 Cache Controller Signals when an uncorrectable metadata event occurs 3 - L2 Cache Controller Signals when a data correction event occurs 4 - L2 Cache Controller Signals when an uncorrectable data event occurs This differs from the SiFive FU540 which only has three L2 cache related interrupts. The sequence in the device tree is defined by an enum: enum {         DIR_CORR = 0,         DATA_CORR,         DATA_UNCORR,         DIR_UNCORR, }; So the correct sequence of the L2 cache interrupts is interrupts = <1>, <3>, <4>, <2>; [Conor] This manifests as an unusable system if the l2-cache driver is enabled, as the wrong interrupt gets cleared & the handler prints errors to the console ad infinitum. Fixes: 0fa6107eca ("RISC-V: Initial DTS for Microchip ICICLE board") CC: stable@vger.kernel.org # 5.15: e35b07a7df: riscv: dts: microchip: mpfs: Group tuples in interrupt properties Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>		2022-08-17 18:39:19 +01:00
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boot	riscv: dts: microchip: correct L2 cache interrupts	2022-08-17 18:39:19 +01:00
configs	riscv: enable Docker requirements in defconfig	2022-07-22 13:43:28 -07:00
errata	riscv: implement Zicbom-based CMO instructions + the t-head variant	2022-08-10 20:49:32 -07:00
include	RISC-V: KVM: Support sstc extension	2022-08-12 07:43:57 -07:00
kernel	RISC-V Patches for the 5.20 Merge Window, Part 2	2022-08-12 18:39:43 -07:00
kvm	RISC-V: KVM: Support sstc extension	2022-08-12 07:43:57 -07:00
lib	riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit	2022-08-10 14:06:31 -07:00
mm	RISC-V: fixups to work with crash tool	2022-08-11 09:04:01 -07:00
net	bpf, riscv: Support riscv jit to provide bpf_line_info	2022-06-02 16:26:01 -07:00
purgatory	riscv/purgatory: Omit use of bin2c	2022-08-11 09:32:34 -07:00
Kbuild	riscv: move errata/ and kvm/ builds to arch/riscv/Kbuild	2022-06-01 22:26:32 -07:00
Kconfig	riscv/purgatory: Omit use of bin2c	2022-08-11 09:32:34 -07:00
Kconfig.debug
Kconfig.erratas	riscv: implement Zicbom-based CMO instructions + the t-head variant	2022-08-10 20:49:32 -07:00
Kconfig.socs	riscv: Kconfig: Style cleanups	2022-06-30 19:26:16 -07:00
Makefile	arch/riscv: add Zihintpause support	2022-08-11 08:03:49 -07:00