Marco Pagani 1e5ec5e90e fpga: altera-pr-ip: fix unsigned comparison with less than zero ... [ Upstream commit 2df84a757d ] Fix the "comparison with less than zero" warning reported by cppcheck for the unsigned (size_t) parameter count of the alt_pr_fpga_write() function. Fixes: d201cc17a8 ("fpga pr ip: Core driver support for Altera Partial Reconfiguration IP") Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Marco Pagani <marpagan@redhat.com> Link: https://lore.kernel.org/r/20220609140520.42662-1-marpagan@redhat.com Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2022-08-17 14:23:41 +02:00
..
altera-cvp.c	fpga: fix spelling mistakes	2021-07-21 19:54:21 -07:00
altera-fpga2sdram.c
altera-freeze-bridge.c	fpga: altera-freeze-bridge: Address warning about unused variable	2021-07-24 15:10:30 -07:00
altera-hps2fpga.c
altera-pr-ip-core-plat.c	fpga: fpga-mgr: altera-pr-ip: Simplify registration	2020-12-01 18:49:32 +01:00
altera-pr-ip-core.c	fpga: altera-pr-ip: fix unsigned comparison with less than zero	2022-08-17 14:23:41 +02:00
altera-ps-spi.c	fpga: fpga-mgr: altera-ps-spi: Simplify registration	2020-12-01 18:49:32 +01:00
dfl-afu-dma-region.c	fpga: dfl: afu: convert get_user_pages() --> pin_user_pages()	2020-06-18 18:12:06 -07:00
dfl-afu-error.c	fpga: dfl: afu: harden port enable logic	2021-03-24 11:15:04 -07:00
dfl-afu-main.c	fpga: dfl: afu: harden port enable logic	2021-03-24 11:15:04 -07:00
dfl-afu-region.c
dfl-afu.h	fpga: dfl: afu: harden port enable logic	2021-03-24 11:15:04 -07:00
dfl-fme-br.c
dfl-fme-error.c	fpga: dfl: fme: add interrupt support for global error reporting	2020-07-06 21:35:42 -07:00
dfl-fme-main.c	fpga: dfl: fme: add interrupt support for global error reporting	2020-07-06 21:35:42 -07:00
dfl-fme-mgr.c	fpga: fpga-mgr: wrap the state() op	2021-07-24 15:10:31 -07:00
dfl-fme-perf.c	fpga: dfl: fme: Fix cpu hotplug issue in performance reporting	2021-07-27 11:05:16 -07:00
dfl-fme-pr.c	fpga: fix spelling mistakes	2021-07-21 19:54:21 -07:00
dfl-fme-pr.h
dfl-fme-region.c	fpga: dfl-fme-region: Use platform_get_drvdata()	2018-11-26 20:47:10 +01:00
dfl-fme.h	fpga: dfl: fme: add performance reporting support	2020-04-28 15:49:28 +02:00
dfl-n3000-nios.c	fpga: fix spelling mistakes	2021-07-21 19:54:21 -07:00
dfl-pci.c	fpga: dfl: pci: add device IDs for Silicom N501x PAC cards	2021-07-24 15:10:30 -07:00
dfl.c	fpga: dfl: Avoid reads to AFU CSRs during enumeration	2021-09-16 15:20:55 -07:00
dfl.h	fpga: dfl: expose feature revision from struct dfl_device	2021-07-29 12:54:10 -07:00
fpga-bridge.c	fpga: fpga-bridge: removed repeated word	2021-07-21 19:54:22 -07:00
fpga-mgr.c	fpga: fpga-mgr: wrap the write_sg() op	2021-07-24 15:10:31 -07:00
fpga-region.c	fpga: region: Rename dev to parent for parent device	2021-06-15 09:29:55 +02:00
ice40-spi.c	fpga: ice40-spi: Add SPI device ID table	2021-09-27 14:00:41 -07:00
Kconfig	FPGA Manager changes for 5.15-rc1	2021-08-05 14:26:03 +02:00
machxo2-spi.c	fpga: machxo2-spi: Fix missing error code in machxo2_write_complete()	2021-09-15 14:01:24 -07:00
Makefile	fpga: versal-fpga: Add versal fpga manager driver	2021-07-21 13:14:09 +02:00
of-fpga-region.c	fpga: of-fpga-region: change FPGA indirect article to an	2021-06-09 14:51:25 +02:00
socfpga-a10.c
socfpga.c	fpga: fpga-mgr: socfpga: Simplify registration	2020-12-01 18:49:32 +01:00
stratix10-soc.c	fpga: fpga-mgr: wrap the state() op	2021-07-24 15:10:31 -07:00
ts73xx-fpga.c	fpga: fpga-mgr: wrap the state() op	2021-07-24 15:10:31 -07:00
versal-fpga.c	fpga: versal-fpga: Remove empty functions	2021-07-27 18:46:03 +02:00
xilinx-pr-decoupler.c	fpga: xilinx-pr-decoupler: Address warning about unused variable	2021-07-24 15:10:30 -07:00
xilinx-spi.c	fpga: xiilnx-spi: Address warning about unused variable	2021-07-24 15:10:30 -07:00
zynq-fpga.c	fpga: fix spelling mistakes	2021-07-21 19:54:21 -07:00
zynqmp-fpga.c	fpga: fpga-mgr: make write_complete() op optional	2021-07-24 15:10:30 -07:00